esavkin
/
web2019
forked from M-Labs/web2019
1
0
Fork 0
Code Pull Requests Activity

refactor(Migen): Reviews layout and md file

This commit is contained in:
sovanna 2019-07-19 15:29:19 +02:00
parent 5c57af1a84
commit 92d7da762b
2 changed files with 55 additions and 64 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

109
content/gateware/migen.md
View File

@ -9,89 +9,74 @@ logo_size = 125
title = "Migen"
+++
{% centerp(safe=true) %}
<h5 class="mb-5">Migen is a Python-based tool that automates further the VLSI design process.</h5>
{% layout_centered_content() %}
##### Migen is a Python-based tool that automates further the VLSI design process.
{% end %}
{% layoutlr1() %}
<div class="row d-flex align-items-center mt-5 mb-5">
{% layout_div(css="col-12 col-md-6") %}
Despite being faster than schematics entry, hardware design with Verilog and VHDL remains tedious and inefficient for several reasons. The event-driven model introduces issues and manual coding that are unnecessary for synchronous circuits, which represent the lion's share of today's logic designs. Counter-intuitive arithmetic rules result in steeper learning curves and provide a fertile ground for subtle bugs in designs. Finally, support for procedural generation of logic (metaprogramming) through "generate" statements is very limited and restricts the ways code can be made generic, reused and organized.
{% end %}
{% layout_div(css="col-12 col-md-6") %}
To address those issues, we have developed the Migen FHDL library that replaces the event-driven paradigm with the notions of combinatorial and synchronous statements, has arithmetic rules that make integers always behave like mathematical integers, and most importantly allows the design's logic to be constructed by a Python program. This last point enables hardware designers to take advantage of the richness of the Python language - object oriented programming, function parameters, generators, operator overloading, libraries, etc. - to build well organized, reusable and elegant designs.
{% end %}
<div class="col-12 col-md-6">
<p>
Despite being faster than schematics entry, hardware design with Verilog and VHDL remains tedious and inefficient for several reasons. The event-driven model introduces issues and manual coding that are unnecessary for synchronous circuits, which represent the lion's share of today's logic designs. Counter-intuitive arithmetic rules result in steeper learning curves and provide a fertile ground for subtle bugs in designs. Finally, support for procedural generation of logic (metaprogramming) through "generate" statements is very limited and restricts the ways code can be made generic, reused and organized.
</p>
</div>
<div class="col-12 col-md-6">
<p>
To address those issues, we have developed the Migen FHDL library that replaces the event-driven paradigm with the notions of combinatorial and synchronous statements, has arithmetic rules that make integers always behave like mathematical integers, and most importantly allows the design's logic to be constructed by a Python program. This last point enables hardware designers to take advantage of the richness of the Python language - object oriented programming, function parameters, generators, operator overloading, libraries, etc. - to build well organized, reusable and elegant designs.
</p>
</div>
{% layout_centered_content(min_width=true) %}
Other Migen libraries are built on FHDL and provide various tools such as a system-on-chip interconnect infrastructure, a dataflow programming system, a more traditional high-level synthesizer that compiles Python routines into state machines with datapaths, and a simulator that allows test benches to be written in Python.
Migen is the foundation for MiSoC.
{% end %}
{% layoutlr1() %}
<div class="col-12 col-md-8 mx-auto">
{% layout_centered_content(min_width=true, force_left=true, card=true) %}
<p class="mt-5">Other Migen libraries are built on FHDL and provide various tools such as a system-on-chip interconnect infrastructure, a dataflow programming system, a more traditional high-level synthesizer that compiles Python routines into state machines with datapaths, and a simulator that allows test benches to be written in Python.</p>
##### More...
<p>Migen is the foundation for MiSoC.</p>
You can find the Migen source <a href="http://github.com/m-labs/migen" target="_blank" rel="noopener noreferrer">here</a>, released under the permissive BSD license.
</div>
**Documentation** (note: sometimes out of date - please help!)
<div class="col-12 col-md-8 mx-auto my-5">
- <a href="https://m-labs.hk/migen/manual" target="_blank" rel="noopener noreferrer">User guide
- <a href="https://m-labs.hk/migen/tutorial.pdf" target="_blank" rel="noopener noreferrer">Tutorial: An introduction to Migen
- <a href="https://m-labs.hk/migen/slides.pdf" target="_blank" rel="noopener noreferrer">Lecture slides
- <a href="https://www.wdj-consulting.com/blog/migen-port.html" target="_blank" rel="noopener noreferrer">Tutorial "Porting a New Board To Migen"</a> by cr1901
- <a href="https://lab.whitequark.org/notes/2016-10-18/implementing-an-uart-in-verilog-and-migen/" target="_blank" rel="noopener noreferrer">"Implementing a UART in Verilog and Migen"</a> by whitequark
- <a href="https://lab.whitequark.org/notes/2016-10-19/implementing-a-simple-soc-in-migen/" target="_blank" rel="noopener noreferrer">"Implementing a simple SoC in Migen"</a> by whitequark
- <a href="http://blog.lambdaconcept.com/doku.php?id=migen:tutorial" target="_blank" rel="noopener noreferrer">Migen Step by Step Tutorial</a> by LambdaConcept
<div class="card shadow py-4 px-3">
<h5 class="mb-1">More...</h5>
<p>You can find the Migen source <a href="http://github.com/m-labs/migen" target="_blank" rel="noopener noreferrer">here</a>, released under the permissive BSD license.</p>
<p class="mb-1"><strong>Documentation</strong> (note: sometimes out of date - please help!)</p>
<ul class="ml-0 mb-0 th">
<li class="pt-2 pb-2"><a href="https://m-labs.hk/migen/manual" target="_blank" rel="noopener noreferrer">User guide</a></li>
<li class="pt-2 pb-2"><a href="https://m-labs.hk/migen/tutorial.pdf" target="_blank" rel="noopener noreferrer">Tutorial: An introduction to Migen</a></li>
<li class="pt-2 pb-2"><a href="https://m-labs.hk/migen/slides.pdf" target="_blank" rel="noopener noreferrer">Lecture slides</a></li>
<li class="pt-2 pb-2"><a href="https://www.wdj-consulting.com/blog/migen-port.html" target="_blank" rel="noopener noreferrer">Tutorial "Porting a New Board To Migen"</a> by cr1901</li>
<li class="pt-2 pb-2"><a href="https://lab.whitequark.org/notes/2016-10-18/implementing-an-uart-in-verilog-and-migen/" target="_blank" rel="noopener noreferrer">"Implementing a UART in Verilog and Migen"</a> by whitequark</li>
<li class="pt-2 pb-2"><a href="https://lab.whitequark.org/notes/2016-10-19/implementing-a-simple-soc-in-migen/" target="_blank" rel="noopener noreferrer">"Implementing a simple SoC in Migen"</a> by whitequark</li>
<li class="pt-2 pb-2"><a href="http://blog.lambdaconcept.com/doku.php?id=migen:tutorial" target="_blank" rel="noopener noreferrer">Migen Step by Step Tutorial</a> by LambdaConcept</li>
</ul>
</div>
</div>
{% end %}
{% layoutlr1() %}
<div class="col-12 col-md-6">
<h5 class="mb-1">MiSoC</h5>
{% layout_text_img(src="images/side-graphic-min.png", alt="", textleft=true, shadow=false) %}
<p>Built on Migen, MiSoC provides a high performance, flexible and lightweight solution to build system-on-chips for various applications.</p>
##### MiSoC
<ul class="ml-0 th">
<li class="pt-2 pb-2">
CPU options:
<ul>
<li class="pt-2 pb-2">LatticeMico32, modified to include an optional MMU (experimental).</li>
<li class="pt-2 pb-2">mor1kx, a better OpenRISC implementation.</li>
</ul>
</li>
<li class="pt-2 pb-2">Memory controller supports SDR, DDR, LPDDR, DDR2 and DDR3.</li>
<li class="pt-2 pb-2">Provided peripherals: UART, GPIO, timer, GPIO, NOR flash controller, SPI flash controller, Ethernet MAC, and more.</li>
<li class="pt-2 pb-2">High performance: on Spartan-6, 83MHz system clock frequencies, 10+Gbps DDR SDRAM bandwidth, 1080p 32bpp framebuffer, etc.</li>
<li class="pt-2 pb-2">Low resource usage: basic implementation fits easily in Spartan-6 LX9.</li>
<li class="pt-2 pb-2">Portable and easy to customize thanks to Python- and Migen-based architecture.</li>
<li class="pt-2 pb-2">Design new peripherals using Migen and benefit from automatic CSR maps and logic, simplified DMAs, etc.</li>
<li class="pt-2 pb-2">Possibility to encapsulate legacy Verilog/VHDL code.</li>
</ul>
<p>The MiSoC source is <a href="http://github.com/m-labs/misoc" target="_blank" rel="noopener noreferrer">here</a>, mostly covered by the permissive BSD license.</p>
</div>
Built on Migen, MiSoC provides a high performance, flexible and lightweight solution to build system-on-chips for various applications.
<div class="d-none d-md-block col-md-6">
<img src="/images/side-graphic-min.png">
</div>
- CPU options:
- LatticeMico32, modified to include an optional MMU (experimental).
- mor1kx, a better OpenRISC implementation.
- Memory controller supports SDR, DDR, LPDDR, DDR2 and DDR3.
- Provided peripherals: UART, GPIO, timer, GPIO, NOR flash controller, SPI flash controller, Ethernet MAC, and more.
- High performance: on Spartan-6, 83MHz system clock frequencies, 10+Gbps DDR SDRAM bandwidth, 1080p 32bpp framebuffer, etc.
- Low resource usage: basic implementation fits easily in Spartan-6 LX9.
- Portable and easy to customize thanks to Python- and Migen-based architecture.
- Design new peripherals using Migen and benefit from automatic CSR maps and logic, simplified DMAs, etc.
- Possibility to encapsulate legacy Verilog/VHDL code.
{% end %}
{% end %}

10
templates/shortcodes/layout_centered_content.html
View File

@ -1,8 +1,14 @@
<div class="{% if css %}{{ css }}{% else %}row d-flex align-items-center mt-5 mb-5{% endif %}">
<div class="{% if min_width %}col-12 col-md-8 mx-auto{% else %}col-12{% endif %} text-center">
<div class="{% if min_width %}col-12 col-md-8 mx-auto{% else %}col-12{% endif %} {% if not force_left %}text-center{% endif %}">
{{ body | markdown | safe }}
{% if card %}
<div class="card shadow py-4 px-3">
{{ body | markdown | safe }}
</div>
{% else %}
{{ body | markdown | safe }}
{% endif %}
</div>