The first ARTIQ core devices used hardware built in-house by physicists (based on a Xilinx KC705 development board with custom FMC cards). To improve the quality, features and scalability of ARTIQ systems, we have been developing the Sinara device family. It provides turnkey control hardware that is reproducible, open, flexible, modular, well-tested, and well-supported by the ARTIQ control software.
The Sinara hardware is in active development, and the latest information is available <ahref="https://github.com/sinara-hw"target="_blank"rel="noopener noreferrer">on the wiki of each project's page</a>. Most of the hardware engineering is done at the <ahref="https://www.ise.pw.edu.pl/"target="_blank"rel="noopener noreferrer">Institute for Electronics Systems</a> at the Warsaw University of Technology.
Kasli and EEMs can be ordered now. We can deliver a rack-mountable crate that contains all the cards, is fully tested, and is ready to be connected to your experiment and computer network. Use our [web-based configuration and ordering tool](../place-order), or contact {{ email(address="sales") }} with your requirements, and we will establish a quote.
One of the main devices in the Sinara family is the 1124 Carrier (codenamed Kasli 2.0). It contains an Artix-7 100T FPGA, DDR3 SDRAM, four SFP connectors, and can control up to 12 daughtercards (Eurocard Extension Module, EEM). The Kasli can act as a stand-alone core device, or as a DRTIO satellite or repeater. The Kasli and its EEMs are installed in one Eurocard 3U chassis. One SFP connector is used for a Gigabit Ethernet connection to your computer network.
Based on a Zynq-7000 SoC, Kasli-SoC can execute kernels on a 1GHz CPU with a hardware FPU. This enables much heavier software computations to be performed on the core device with a low-latency path to the experiment. Network transfer rates are also greatly increased. Features are otherwise similar as Kasli's.
See our paper <ahref="https://arxiv.org/abs/2111.15290"target="_blank"rel="noopener noreferrer">Combining processing throughput, low latency and timing accuracy in experiment control</a> for information about what Kasli-SoC enables compared to previous ARTIQ platforms.
For simple TTL signals, we offer I/O cards in the EEM form factor with 8 channels over BNC (2118), SMA (2128) or MCX (2138) connectors. The IOs are divided into two banks of 4, with per-bank ground isolation. The direction (input/output) and termination (high-Z/50Ω) is selectable on a per-channel basis via I2C or on-board switches. The open circuit voltage of outputs is 5V, and outputs can supply a valid TTL level into 50Ω and tolerate an indefinite short circuit to ground.
When higher densities or faster speeds are required, the Sinara 2238 MCX card is available. It provides 16 non-isolated channels in 4hp of space using MCX connectors. The card is bidirectional, with the direction controlled in groups of 4 channels. Each IO can be individually terminated with 50Ω.
Each RJ45 supplies 4 LVDS DIOs. The direction (input/output) is individually selectable for each signal via on-board switches. Outputs are intended to drive 100Ω loads (LVDS is short-circuit protected), inputs are 100Ω terminated. The connectors dedicate all 8 pins to LVDS signals, ground is on the connector shield so only shielded Ethernet cat 6 shielded cables are allowed.
Banker is a versatile 128-channel TTL GPIO module. It has flexible connectivity and contains a small Lattice iCE40 FPGA, supported by Yosys and IceStorm.
All outputs can be configured either as 3.3 or 5V. They can drive 50Ω load when set to 5V. FPGA can is configured from on-board FLASH. FLASH can be updated over I2C or with the on-board SPI connector.
The VHDCI connections can be used to interface with either non-buffered or buffered remote boards that distribute signals to neighboring modules. These modules can be assembled together and placed in COTS enclosures. The enclosures fit onto the low-cost and simple DIN rail standard.
There are several DIN-rail compatible modules for use with Banker. They are interconnected using edge connectors and can be configured as mix of 4 modules of following type:
**Note:** While Banker can be used currently if you program the FPGA yourself, turn-key support from within ARTIQ is currently not available or funded. Contact us if you would like to sponsor this project.
Urukul is a 4 channel DDS-based frequency synthesizer for the EEM form factor. It provides sub-Hz frequency resolution, controlled phase steps, and accurate output amplitude control. We offer it in two variants, with either the AD9910 (Sinara 4410) or the AD9912 (Sinara 4412) chip. AD9910- and AD9912-based cards can be freely mixed in the same ARTIQ system with no particular issues.
With the SU-Servo feature of ARTIQ, the 4410 DDS (which has fine amplitude control, unlike the 4412) can be used in combination with the 5108 Sampler to form a laser intensity servo. In this application, the Urukul card drives AOMs and photodiodes are connected to Sampler to monitor laser intensities. When ordering your system, specify that you want SU-Servo integrated into the gateware.
In regular mode, various DDS features are supported, including frequency, phase and amplitude control, and AD9910 RAM mode. See the ARTIQ manual for more details.
Like the Urukul DDS but with a VCO/PLL (ADF5356) as the synthesizer and options for frequency double/tripler and analog frontend mezzanines, e.g. Sinara 4457 "Almazny".
- Much larger frequency range (53 MHz to >4 GHz vs. ~1 MHz to 500 MHz in the first Nyquist zone for Urukul). Up to 13.6 GHz when using the mezzanine.
- Much higher frequency resolution.
- Lower jitter and phase noise.
- No linear high resolution output amplitude setting (c.f. AD9910 ASF).
- No deterministic phase control, no coherent or absolute phase changes.
- Large frequency changes are not "agile" (take a few ms) and do not have high timing resolution; small frequency changes (<10kHz)canstillbemaderapidly.
- RF switch changes or attenuator changes still benefit from high timing resolution through the EEM connector.
Zotino connects the 32 channels to both (a) a HD68 connector on its front panel and (b) to four IDC connectors on the board. Each IDC connection with 8 channels can be broken out to BNC or SMA using BNC-IDC or SMA-IDC respectively.
- The temperature of the Zotino DAC can be stabilized using the [Sinara 8451 Thermostat](../control-loops) to reduce output voltage drifts. A stable temperature can be re-established quickly after momentary disruption.
- Zotino was placed on a table without protection from air currents, and an air conditioning unit generating disturbances nearby. The graph show its the temperature stability over 5 minutes while connected to the [Sinara Thermostat](../control-loops).
Fastino is a higher-speed version of Zotino. It also has 32 16-bit channels, but they all can be updated at 2Msps simultaneously (1Gb/s data).
Note that reaching this maximum hardware speed requires gateware acceleration; naively pushing samples one by one from a software ARTIQ-Python kernel results in a much lower update rate.
The Sinara 5108 is an 8-channel, 16-bit ADC EEM with an update rate of up to 1.5MSPS (all channels simultaneously). It has low-noise differential front end with a digitally programmable gain, providing full-scale input ranges between +-10mV (G=1000) and +-10V (G=1).
In SU-Servo mode, the 5108 Sampler can be used in combination with the 4410 DDS to form a laser intensity servo. Otherwise, in regular mode, single sample values can be read out by ARTIQ kernels (due to CPU overhead, the actual sample rate in regular mode is reduced).
Note that update rate specification on this page is for the hardware only; ARTIQ kernel and RTIO overhead make the effective sample rate lower. Typically, only with gateware (e.g. SU-Servo) can the maximum bandwidth be achieved. SU-Servo is part of the regular ARTIQ firmware; development of other gateware can be purchased separately.
In the FPGA, frame data streamed through "ROI engines". Each ROI engine gates on one rectangular pixel region and accumulates pixel values for each frame. The ROI engines operate independently and can be overlapping. After the frame, the accumulated value is pushed as an RTIO input event. Regions of interest (ROI) can be configured at runtime, and are defined with the computer.
The Sinara 7210 is a low-noise clock distribution module that can be used to distribute low jitter clock signal among 3U boards. 2 inputs, 10 outputs including 4 SMAs, frequency up to 1GHz, low jitter <100fsRMS.
- up to 16 dynamic tones per channel using <ahref="https://github.com/quartiq/miqro-sim"target="_blank"rel="noopener noreferrer">MIQRO gateware</a> (available separately from QUARTIQ).
- 31.5 dB range digital step attenuator (similar to Urukul).
- 2 channels of 5 MS/s ADC (similar to Sampler).
- Artix-7 FPGA.
- Internal MMCX clock from Kasli/Clocker and external SMA.
- Upconverter is optional.
- DDR3 SDRAM (currently not used by gateware).
- The gateware support is currently limited to the <ahref="https://github.com/quartiq/Phaser_STFT_Pulsegen"target="_blank"rel="noopener noreferrer">STFT pulse generator</a>. Other applications are possible in theory (including arbitrary waveform buffer in SDRAM), please contact us.
We can deliver a rack-mountable crate that contains all the cards, is fully tested, and is ready to be connected to your experiment and computer network. The lead time can be as short as a few working days and we will provide assistance to help you set up your new equipment with ARTIQ via the online helpdesk. Using our AFWS tool, you can keep the firmware of your M-Labs devices up-to-date easily, and benefit from the new features we continuously develop into ARTIQ.
Use our [web-based configuration and ordering tool](../place-order), or contact {{ email(address="sales") }} with your requirements, and we will establish a quote.
