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The free and open dissemination of methods and results is central to scientific progress.

The ARTIQ and Sinara authors, contributors, and supporters consider the free and open exchange of scientific tools to be equally important and have chosen the licensing terms of ARTIQ and Sinara accordingly. ARTIQ, including its gateware, the firmware, and the ARTIQ tools and libraries are licensed as LGPLv3+. The Sinara hardware designs are licensed under CERN OHL.
This ensures that a user of ARTIQ or Sinara hardware designs obtains broad rights to use, redistribute, study, and modify them.

ARTIQ and the related components that we are developing ([Migen/MiSoC](/gateware/migen), [nMigen](/gateware/nmigen), [smoltcp](/software/smoltcp), [minimq](https://github.com/quartiq/minimq), [zynq-rs](https://git.m-labs.hk/m-labs/zynq-rs), [SiPyCo](https://github.com/m-labs/sipyco), [RayOpt](https://github.com/quartiq/rayopt), [WFVM](https://git.m-labs.hk/m-labs/wfvm), ...) need to be kept on a sound financial basis. We have been relying on a combination of [hardware sales](../place-order), sponsorships, and grants.

##### Sponsors

We acknowledge support from our partners below. Please get in touch (sales@m-\*\*\*.hk) if you also want to move ARTIQ forward!

###### Platinum level

[![log nist](/images/logo_nist.png)](https://www.nist.gov/pml/time-and-frequency-division/ion-storage)

ARTIQ was initiated by the [Ion Storage Group](https://www.nist.gov/pml/time-and-frequency-division/ion-storage) at NIST, who provided valuable technical insight as well as financial support to develop the first version of the ARTIQ software and gateware targeting the KC705 development kit. This included some FPGA SoC libraries such as a SDRAM controller and PHYs, the first two iterations of the ARTIQ runtime including the development of [smoltcp](/software/smoltcp), the RTIO infrastructure and PHYs, the ARTIQ-Python LLVM-based compiler, RTIO DMA, the ARTIQ dashboard and browser, the ARTIQ master, and several controllers. They also supported the more recent ARTIQ port to Zynq, targeting the ZC706 development kit, and enabling ARTIQ-Python kernels to take advantage of the 1GHz CPU in the core device; as well as matrix and trigonometric function support in ARTIQ-Python kernels.
<small>*Disclaimer: NIST and the United States government are not providing an endorsement of ARTIQ.*</small>

[![logo oxford](/images/logo_oxford.png)](https://www2.physics.ox.ac.uk/research/ion-trap-quantum-computing-group)

The [University of Oxford](https://www2.physics.ox.ac.uk/research/ion-trap-quantum-computing-group) funded major improvements to the RTIO infrastructure: the Distributed RTIO (DRTIO) system that allows clock synchronization and RTIO command transfer between FPGAs using cost-effective high-speed serial links (e.g. over fiber optics), and changes to the RTIO architecture to improve scalability. They also funded the Sinara Sampler hardware and software, the [SU-Servo](https://m-labs.hk/artiq/manual-beta/core_drivers_reference.html?highlight=suservo#artiq.coredevice.suservo.SUServo) integrated laser intensity servo, parts of Urukul and Zotino, firmware development on the Sinara Thermostat, the Kasli v2.0 ARTIQ support, the Fastino ARTIQ support, parts of the Sinara Phaser gateware and software development, and significant parts of the Booster RF amplifier.

[![logo wut](/images/logo_wut.png)](http://www.ise.pw.edu.pl)

[Warsaw University of Technology](http://www.ise.pw.edu.pl) contributed most of the hardware designs and prototypes for the Sinara ecosystem.

###### Gold level

[![logo oregon](/images/logo_oregon.png)](https://ions.uoregon.edu/)

The [University of Oregon](https://ions.uoregon.edu/) funded a large part of the Sinara Phaser gateware and software development, as well as firmware for the Pounder PDH/phase lock signal generator for Stabilizer.

[![logo arl](/images/logo_arl_devcom.png)](http://brittonlab.umd.edu/)

The [Army Research Lab](http://brittonlab.umd.edu/) funded the SAWG high-throughput digital waveform generator, as well as ARTIQ support for the Sayma and Metlino boards.


###### Silver level

[![logo quest](/images/logo_luh.png)](https://www.quest-lfs.uni-hannover.de/)

[QUEST/Uni Hannover](https://www.quest-lfs.uni-hannover.de/) funded gateware and software support for the Grabber EEM, partial Mirny support, part of the Fastino development, and part of Urukul synchronization support.

[![logo ptb](/images/logo_ptb.png)](http://ptb.de)

PTB funded the development of lock-in amplifier support for the Sinara Stabilizer, as well as part of Urukul synchronization support.

[![logo uwisc](/images/logo_uwisc.png)](http://hexagon.physics.wisc.edu/)

The [University of Wisconsin-Madison](http://hexagon.physics.wisc.edu/) funded the development of Urukul RAM mode support.

[MIT](http://web.mit.edu/~cua/www/quanta/) funded parts of the Sinara Phaser gateware and software development.

[![logo hu](/images/logo_hu.png)](https://www.physik.hu-berlin.de/en/qom/people/qom-group/markus/view)

[Humboldt University of Berlin](https://www.physik.hu-berlin.de/en/qom/people/qom-group/markus/view) funded [prototype digital spectroscopy modulation/demodulation firmware](https://github.com/quartiq/queenmod), which is part of the "Optical quantum technologies on nanosatellites" (QUEEN) project.

##### Grants

Parts of ARTIQ and Sinara have been developed through the participation of our sister company QUARTIQ GmbH in European research grant programmes.

[![logo opticlock](/images/logo_opticlock.png)](https://www.opticlock.de/)

The BMBF project [Opticlock](https://www.opticlock.de/) developed an optical clock as a replacement for a hydrogen maser, based on a single ytterbium ion captured and laser-cooled in an ion trap. It helped fund the development of the Kasli, Urukul, Zotino and Sampler modules.

![logo aiartiq](/images/logo_aiartiq.png)

AI-ARTIQ develops a control platform for laser sources and atom interferometer-based quantum sensors.
