From fed3e767e97aecb0caa98ff20473fbc04d1d33a1 Mon Sep 17 00:00:00 2001 From: Astro Date: Thu, 12 Mar 2020 19:24:57 +0100 Subject: [PATCH] pins: setup dac spi 0,1 --- src/main.rs | 4 +-- src/pins.rs | 80 ++++++++++++++++++++++++++++++++++++++++++++++++----- 2 files changed, 75 insertions(+), 9 deletions(-) diff --git a/src/main.rs b/src/main.rs index 22647b8..84b7998 100644 --- a/src/main.rs +++ b/src/main.rs @@ -80,8 +80,8 @@ fn main() -> ! { let pins = Pins::setup( clocks, dp.TIM1, dp.TIM3, - dp.GPIOA, dp.GPIOB, dp.GPIOC, dp.GPIOE, dp.GPIOG, - dp.SPI2 + dp.GPIOA, dp.GPIOB, dp.GPIOC, dp.GPIOE, dp.GPIOF, dp.GPIOG, + dp.SPI2, dp.SPI4, dp.SPI5 ); let mut adc = ad7172::Adc::new(pins.adc_spi, pins.adc_nss).unwrap(); diff --git a/src/pins.rs b/src/pins.rs index 48f2ad9..bf0b43f 100644 --- a/src/pins.rs +++ b/src/pins.rs @@ -1,3 +1,7 @@ +use embedded_hal::{ + blocking::spi::Transfer, + digital::v2::OutputPin, +}; use stm32f4xx_hal::{ gpio::{ AF5, Alternate, @@ -5,6 +9,7 @@ use stm32f4xx_hal::{ gpiob::*, gpioc::*, gpioe::*, + gpiof::*, gpiog::*, GpioExt, Output, PushPull, @@ -12,19 +17,27 @@ use stm32f4xx_hal::{ }, rcc::Clocks, pwm::{self, PwmChannels}, - spi::Spi, - stm32::{GPIOA, GPIOB, GPIOC, GPIOE, GPIOG, SPI2, TIM1, TIM3}, - time::{U32Ext, Hertz}, + spi::{self, Spi, NoMiso}, + stm32::{GPIOA, GPIOB, GPIOC, GPIOE, GPIOF, GPIOG, SPI2, SPI4, SPI5, TIM1, TIM3}, + time::{U32Ext, Hertz, MegaHertz}, }; /// SPI peripheral used for communication with the ADC type AdcSpi = Spi>, PB14>, PB15>)>; +type Dac0Spi = Spi>, NoMiso, PE6>)>; +type Dac1Spi = Spi>, NoMiso, PF9>)>; + +const DAC_FREQ: MegaHertz = MegaHertz(30); pub struct Pins { pub adc_spi: AdcSpi, pub adc_nss: PB12>, pub pwm: PwmPins, + pub dac0_spi: Dac0Spi, + pub dac0_sync: PE4>, + pub dac1_spi: Dac1Spi, + pub dac1_sync: PF6>, } impl Pins { @@ -33,13 +46,14 @@ impl Pins { clocks: Clocks, tim1: TIM1, tim3: TIM3, - gpioa: GPIOA, gpiob: GPIOB, gpioc: GPIOC, gpioe: GPIOE, gpiog: GPIOG, - spi2: SPI2 + gpioa: GPIOA, gpiob: GPIOB, gpioc: GPIOC, gpioe: GPIOE, gpiof: GPIOF, gpiog: GPIOG, + spi2: SPI2, spi4: SPI4, spi5: SPI5 ) -> Self { let gpioa = gpioa.split(); let gpiob = gpiob.split(); let gpioc = gpioc.split(); let gpioe = gpioe.split(); + let gpiof = gpiof.split(); let gpiog = gpiog.split(); Self::setup_ethernet( @@ -50,6 +64,15 @@ impl Pins { let adc_spi = Self::setup_spi_adc(clocks, spi2, gpiob.pb10, gpiob.pb14, gpiob.pb15); let adc_nss = gpiob.pb12.into_push_pull_output(); + let (dac0_spi, dac0_sync) = Self::setup_dac0( + clocks, spi4, + gpioe.pe2, gpioe.pe4, gpioe.pe6 + ); + let (dac1_spi, dac1_sync) = Self::setup_dac1( + clocks, spi5, + gpiof.pf7, gpiof.pf6, gpiof.pf9 + ); + let pwm = PwmPins::setup( clocks, tim1, tim3, gpioc.pc6, gpioc.pc7, @@ -58,9 +81,10 @@ impl Pins { ); Pins { - adc_spi, - adc_nss, + adc_spi, adc_nss, pwm, + dac0_spi, dac0_sync, + dac1_spi, dac1_sync, } } @@ -85,6 +109,48 @@ impl Pins { ) } + fn setup_dac0( + clocks: Clocks, spi4: SPI4, + sclk: PE2, sync: PE4, sdin: PE6 + ) -> (Dac0Spi, PE4>) { + let sclk = sclk.into_alternate_af5(); + let sdin = sdin.into_alternate_af5(); + let spi = Spi::spi4( + spi4, + (sclk, NoMiso, sdin), + spi::Mode { + polarity: spi::Polarity::IdleHigh, + phase: spi::Phase::CaptureOnSecondTransition, + }, + DAC_FREQ.into(), + clocks + ); + let sync = sync.into_push_pull_output(); + + (spi, sync) + } + + fn setup_dac1( + clocks: Clocks, spi5: SPI5, + sclk: PF7, sync: PF6, sdin: PF9 + ) -> (Dac1Spi, PF6>) { + let sclk = sclk.into_alternate_af5(); + let sdin = sdin.into_alternate_af5(); + let spi = Spi::spi5( + spi5, + (sclk, NoMiso, sdin), + spi::Mode { + polarity: spi::Polarity::IdleHigh, + phase: spi::Phase::CaptureOnSecondTransition, + }, + DAC_FREQ.into(), + clocks + ); + let sync = sync.into_push_pull_output(); + + (spi, sync) + } + /// Configure the GPIO pins for Ethernet operation fn setup_ethernet( pa1: PA1, pa2: PA2, pc1: PC1, pa7: PA7,