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pins: setup PwmPins

This commit is contained in:
Astro 2020-03-12 17:26:14 +01:00
parent ac336b7a26
commit f021ebd6e6
4 changed files with 83 additions and 21 deletions
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17
Cargo.lock generated
View File

@ -209,12 +209,6 @@ version = "0.2.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "e2a38df5b15c8d5c7e8654189744d8e396bddc18ad48041a500ce52d6948941f"
[[package]]
name = "rand_core"
version = "0.5.1"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "90bde5296fc891b0cef12a6d03ddccc162ce7b2aff54160af9338f8d40df6d19"
[[package]]
name = "rustc_version"
version = "0.2.3"
@ -260,7 +254,6 @@ checksum = "dba1a27d3efae4351c8051072d619e3ade2820635c3958d826bfea39d59b54c8"
[[package]]
name = "stm32-eth"
version = "0.1.2"
source = "git+https://github.com/stm32-rs/stm32-eth.git#2c5dce379b85a31fb0b9c58a028b6454be1727aa"
dependencies = [
"aligned",
"log",
@ -271,9 +264,9 @@ dependencies = [
[[package]]
name = "stm32f4"
version = "0.10.0"
version = "0.9.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "44a3d6c58b14e63926273694e7dd644894513c5e35ce6928c4657ddb62cae976"
checksum = "88640ad08c62e0651a1320187f38c3655d025ed580a10f0e4d85a2cc4829069f"
dependencies = [
"bare-metal",
"cortex-m",
@ -283,9 +276,8 @@ dependencies = [
[[package]]
name = "stm32f4xx-hal"
version = "0.7.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "54abcca9b4abfb0d0518591ea39c2e14a0b07b9791548d4516ab5e61a83067cc"
version = "0.6.0"
source = "git+https://github.com/thalesfragoso/stm32f4xx-hal?branch=pwm-impl#ef939935b90581553dc03f9146d05510b3ceba58"
dependencies = [
"bare-metal",
"cast",
@ -293,7 +285,6 @@ dependencies = [
"cortex-m-rt",
"embedded-hal",
"nb",
"rand_core",
"stm32f4",
"void",
]

3
Cargo.toml
View File

@ -22,7 +22,8 @@ cortex-m = "0.6"
cortex-m-rt = { version = "0.6", features = ["device"] }
cortex-m-log = { version = "0.6", features = ["log-integration"] }
embedded-hal = "0.2"
stm32f4xx-hal = { version = "0.7", features = ["rt", "stm32f427"] }
# TODO: pending https://github.com/stm32-rs/stm32f4xx-hal/pull/125
stm32f4xx-hal = { git = "https://github.com/thalesfragoso/stm32f4xx-hal", branch = "pwm-impl", features = ["rt", "stm32f427"] }
stm32-eth = { version = "0.1.2", features = ["smoltcp-phy"], git = "https://github.com/stm32-rs/stm32-eth.git" }
smoltcp = { version = "0.6.0", default-features = false, features = ["proto-ipv4", "socket-tcp", "log"] }
hash2hwaddr = { version = "0.0", optional = true }

6
src/main.rs
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@ -73,7 +73,11 @@ fn main() -> ! {
wd.start(WATCHDOG_INTERVAL.ms());
wd.feed();
let pins = Pins::setup(clocks, dp.GPIOA, dp.GPIOB, dp.GPIOC, dp.GPIOG, dp.SPI2);
let pins = Pins::setup(
clocks, dp.TIM1, dp.TIM3,
dp.GPIOA, dp.GPIOB, dp.GPIOC, dp.GPIOE, dp.GPIOG,
dp.SPI2
);
let mut adc = ad7172::Adc::new(pins.adc_spi, pins.adc_nss).unwrap();

78
src/pins.rs
View File

@ -1,17 +1,20 @@
use stm32f4xx_hal::{
gpio::{
AF5, Alternate,
gpioa::{PA1, PA2, PA7},
gpiob::{PB10, PB11, PB12, PB13, PB14, PB15},
gpioc::{PC1, PC4, PC5},
gpiog::{PG13},
gpioa::*,
gpiob::*,
gpioc::*,
gpioe::*,
gpiog::*,
GpioExt,
Output, PushPull,
Speed::VeryHigh,
},
rcc::Clocks,
pwm::{self, PwmChannels},
spi::Spi,
stm32::{GPIOA, GPIOB, GPIOC, GPIOG, SPI2},
stm32::{GPIOA, GPIOB, GPIOC, GPIOE, GPIOG, SPI2, TIM1, TIM3},
time::{U32Ext, Hertz},
};
@ -21,14 +24,22 @@ type AdcSpi = Spi<SPI2, (PB10<Alternate<AF5>>, PB14<Alternate<AF5>>, PB15<Altern
pub struct Pins {
pub adc_spi: AdcSpi,
pub adc_nss: PB12<Output<PushPull>>,
pub pwm: PwmPins,
}
impl Pins {
/// Setup GPIO pins and configure MCU peripherals
pub fn setup(clocks: Clocks, gpioa: GPIOA, gpiob: GPIOB, gpioc: GPIOC, gpiog: GPIOG, spi2: SPI2) -> Self {
pub fn setup(
clocks: Clocks,
tim1: TIM1,
tim3: TIM3,
gpioa: GPIOA, gpiob: GPIOB, gpioc: GPIOC, gpioe: GPIOE, gpiog: GPIOG,
spi2: SPI2
) -> Self {
let gpioa = gpioa.split();
let gpiob = gpiob.split();
let gpioc = gpioc.split();
let gpioe = gpioe.split();
let gpiog = gpiog.split();
Self::setup_ethernet(
@ -38,9 +49,18 @@ impl Pins {
);
let adc_spi = Self::setup_spi_adc(clocks, spi2, gpiob.pb10, gpiob.pb14, gpiob.pb15);
let adc_nss = gpiob.pb12.into_push_pull_output();
let pwm = PwmPins::setup(
clocks, tim1, tim3,
gpioc.pc6, gpioc.pc7,
gpioe.pe9, gpioe.pe11,
gpioe.pe13, gpioe.pe14
);
Pins {
adc_spi,
adc_nss,
pwm,
}
}
@ -91,3 +111,49 @@ impl Pins {
pb13.into_alternate_af11().set_speed(VeryHigh);
}
}
pub struct PwmPins {
max_v0: PwmChannels<TIM3, pwm::C1>,
max_v1: PwmChannels<TIM3, pwm::C2>,
max_i_pos0: PwmChannels<TIM1, pwm::C1>,
max_i_pos1: PwmChannels<TIM1, pwm::C2>,
max_i_neg0: PwmChannels<TIM1, pwm::C3>,
max_i_neg1: PwmChannels<TIM1, pwm::C4>,
}
impl PwmPins {
fn setup<M1, M2, M3, M4, M5, M6>(
clocks: Clocks,
tim1: TIM1,
tim3: TIM3,
max_v0: PC6<M1>,
max_v1: PC7<M2>,
max_i_pos0: PE9<M3>,
max_i_pos1: PE11<M4>,
max_i_neg0: PE13<M5>,
max_i_neg1: PE14<M6>,
) -> PwmPins {
let freq = 20u32.khz();
let channels = (
max_v0.into_alternate_af2(),
max_v1.into_alternate_af2(),
);
let (max_v0, max_v1) = pwm::tim3(tim3, channels, clocks, freq);
let channels = (
max_i_pos0.into_alternate_af1(),
max_i_pos1.into_alternate_af1(),
max_i_neg0.into_alternate_af1(),
max_i_neg1.into_alternate_af1(),
);
let (max_i_pos0, max_i_pos1, max_i_neg0, max_i_neg1) =
pwm::tim1(tim1, channels, clocks, freq);
PwmPins {
max_v0, max_v1,
max_i_pos0, max_i_pos1,
max_i_neg0, max_i_neg1,
}
}
}