forked from M-Labs/thermostat
pins: setup PwmPins
This commit is contained in:
parent
ac336b7a26
commit
f021ebd6e6
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@ -209,12 +209,6 @@ version = "0.2.2"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "e2a38df5b15c8d5c7e8654189744d8e396bddc18ad48041a500ce52d6948941f"
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checksum = "e2a38df5b15c8d5c7e8654189744d8e396bddc18ad48041a500ce52d6948941f"
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[[package]]
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name = "rand_core"
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version = "0.5.1"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "90bde5296fc891b0cef12a6d03ddccc162ce7b2aff54160af9338f8d40df6d19"
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[[package]]
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[[package]]
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name = "rustc_version"
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name = "rustc_version"
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version = "0.2.3"
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version = "0.2.3"
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@ -260,7 +254,6 @@ checksum = "dba1a27d3efae4351c8051072d619e3ade2820635c3958d826bfea39d59b54c8"
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[[package]]
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[[package]]
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name = "stm32-eth"
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name = "stm32-eth"
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version = "0.1.2"
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version = "0.1.2"
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source = "git+https://github.com/stm32-rs/stm32-eth.git#2c5dce379b85a31fb0b9c58a028b6454be1727aa"
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dependencies = [
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dependencies = [
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"aligned",
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"aligned",
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"log",
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"log",
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@ -271,9 +264,9 @@ dependencies = [
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[[package]]
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[[package]]
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name = "stm32f4"
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name = "stm32f4"
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version = "0.10.0"
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version = "0.9.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "44a3d6c58b14e63926273694e7dd644894513c5e35ce6928c4657ddb62cae976"
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checksum = "88640ad08c62e0651a1320187f38c3655d025ed580a10f0e4d85a2cc4829069f"
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dependencies = [
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dependencies = [
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"bare-metal",
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"bare-metal",
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"cortex-m",
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"cortex-m",
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@ -283,9 +276,8 @@ dependencies = [
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[[package]]
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[[package]]
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name = "stm32f4xx-hal"
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name = "stm32f4xx-hal"
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version = "0.7.0"
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version = "0.6.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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source = "git+https://github.com/thalesfragoso/stm32f4xx-hal?branch=pwm-impl#ef939935b90581553dc03f9146d05510b3ceba58"
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checksum = "54abcca9b4abfb0d0518591ea39c2e14a0b07b9791548d4516ab5e61a83067cc"
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dependencies = [
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dependencies = [
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"bare-metal",
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"bare-metal",
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"cast",
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"cast",
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@ -293,7 +285,6 @@ dependencies = [
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"cortex-m-rt",
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"cortex-m-rt",
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"embedded-hal",
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"embedded-hal",
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"nb",
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"nb",
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"rand_core",
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"stm32f4",
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"stm32f4",
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"void",
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"void",
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]
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]
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@ -22,7 +22,8 @@ cortex-m = "0.6"
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cortex-m-rt = { version = "0.6", features = ["device"] }
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cortex-m-rt = { version = "0.6", features = ["device"] }
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cortex-m-log = { version = "0.6", features = ["log-integration"] }
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cortex-m-log = { version = "0.6", features = ["log-integration"] }
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embedded-hal = "0.2"
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embedded-hal = "0.2"
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stm32f4xx-hal = { version = "0.7", features = ["rt", "stm32f427"] }
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# TODO: pending https://github.com/stm32-rs/stm32f4xx-hal/pull/125
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stm32f4xx-hal = { git = "https://github.com/thalesfragoso/stm32f4xx-hal", branch = "pwm-impl", features = ["rt", "stm32f427"] }
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stm32-eth = { version = "0.1.2", features = ["smoltcp-phy"], git = "https://github.com/stm32-rs/stm32-eth.git" }
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stm32-eth = { version = "0.1.2", features = ["smoltcp-phy"], git = "https://github.com/stm32-rs/stm32-eth.git" }
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smoltcp = { version = "0.6.0", default-features = false, features = ["proto-ipv4", "socket-tcp", "log"] }
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smoltcp = { version = "0.6.0", default-features = false, features = ["proto-ipv4", "socket-tcp", "log"] }
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hash2hwaddr = { version = "0.0", optional = true }
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hash2hwaddr = { version = "0.0", optional = true }
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@ -73,7 +73,11 @@ fn main() -> ! {
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wd.start(WATCHDOG_INTERVAL.ms());
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wd.start(WATCHDOG_INTERVAL.ms());
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wd.feed();
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wd.feed();
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let pins = Pins::setup(clocks, dp.GPIOA, dp.GPIOB, dp.GPIOC, dp.GPIOG, dp.SPI2);
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let pins = Pins::setup(
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clocks, dp.TIM1, dp.TIM3,
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dp.GPIOA, dp.GPIOB, dp.GPIOC, dp.GPIOE, dp.GPIOG,
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dp.SPI2
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);
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let mut adc = ad7172::Adc::new(pins.adc_spi, pins.adc_nss).unwrap();
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let mut adc = ad7172::Adc::new(pins.adc_spi, pins.adc_nss).unwrap();
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78
src/pins.rs
78
src/pins.rs
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@ -1,17 +1,20 @@
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use stm32f4xx_hal::{
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use stm32f4xx_hal::{
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gpio::{
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gpio::{
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AF5, Alternate,
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AF5, Alternate,
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gpioa::{PA1, PA2, PA7},
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gpioa::*,
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gpiob::{PB10, PB11, PB12, PB13, PB14, PB15},
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gpiob::*,
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gpioc::{PC1, PC4, PC5},
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gpioc::*,
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gpiog::{PG13},
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gpioe::*,
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gpiog::*,
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GpioExt,
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GpioExt,
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Output, PushPull,
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Output, PushPull,
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Speed::VeryHigh,
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Speed::VeryHigh,
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},
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},
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rcc::Clocks,
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rcc::Clocks,
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pwm::{self, PwmChannels},
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spi::Spi,
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spi::Spi,
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stm32::{GPIOA, GPIOB, GPIOC, GPIOG, SPI2},
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stm32::{GPIOA, GPIOB, GPIOC, GPIOE, GPIOG, SPI2, TIM1, TIM3},
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time::{U32Ext, Hertz},
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};
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};
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@ -21,14 +24,22 @@ type AdcSpi = Spi<SPI2, (PB10<Alternate<AF5>>, PB14<Alternate<AF5>>, PB15<Altern
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pub struct Pins {
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pub struct Pins {
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pub adc_spi: AdcSpi,
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pub adc_spi: AdcSpi,
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pub adc_nss: PB12<Output<PushPull>>,
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pub adc_nss: PB12<Output<PushPull>>,
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pub pwm: PwmPins,
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}
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}
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impl Pins {
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impl Pins {
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/// Setup GPIO pins and configure MCU peripherals
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/// Setup GPIO pins and configure MCU peripherals
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pub fn setup(clocks: Clocks, gpioa: GPIOA, gpiob: GPIOB, gpioc: GPIOC, gpiog: GPIOG, spi2: SPI2) -> Self {
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pub fn setup(
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clocks: Clocks,
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tim1: TIM1,
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tim3: TIM3,
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gpioa: GPIOA, gpiob: GPIOB, gpioc: GPIOC, gpioe: GPIOE, gpiog: GPIOG,
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spi2: SPI2
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) -> Self {
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let gpioa = gpioa.split();
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let gpioa = gpioa.split();
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let gpiob = gpiob.split();
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let gpiob = gpiob.split();
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let gpioc = gpioc.split();
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let gpioc = gpioc.split();
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let gpioe = gpioe.split();
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let gpiog = gpiog.split();
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let gpiog = gpiog.split();
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Self::setup_ethernet(
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Self::setup_ethernet(
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@ -38,9 +49,18 @@ impl Pins {
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);
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);
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let adc_spi = Self::setup_spi_adc(clocks, spi2, gpiob.pb10, gpiob.pb14, gpiob.pb15);
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let adc_spi = Self::setup_spi_adc(clocks, spi2, gpiob.pb10, gpiob.pb14, gpiob.pb15);
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let adc_nss = gpiob.pb12.into_push_pull_output();
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let adc_nss = gpiob.pb12.into_push_pull_output();
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let pwm = PwmPins::setup(
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clocks, tim1, tim3,
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gpioc.pc6, gpioc.pc7,
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gpioe.pe9, gpioe.pe11,
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gpioe.pe13, gpioe.pe14
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);
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Pins {
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Pins {
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adc_spi,
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adc_spi,
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adc_nss,
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adc_nss,
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pwm,
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}
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}
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}
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}
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@ -91,3 +111,49 @@ impl Pins {
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pb13.into_alternate_af11().set_speed(VeryHigh);
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pb13.into_alternate_af11().set_speed(VeryHigh);
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}
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}
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}
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}
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pub struct PwmPins {
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max_v0: PwmChannels<TIM3, pwm::C1>,
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max_v1: PwmChannels<TIM3, pwm::C2>,
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max_i_pos0: PwmChannels<TIM1, pwm::C1>,
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max_i_pos1: PwmChannels<TIM1, pwm::C2>,
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max_i_neg0: PwmChannels<TIM1, pwm::C3>,
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max_i_neg1: PwmChannels<TIM1, pwm::C4>,
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}
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impl PwmPins {
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fn setup<M1, M2, M3, M4, M5, M6>(
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clocks: Clocks,
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tim1: TIM1,
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tim3: TIM3,
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max_v0: PC6<M1>,
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max_v1: PC7<M2>,
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max_i_pos0: PE9<M3>,
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max_i_pos1: PE11<M4>,
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max_i_neg0: PE13<M5>,
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max_i_neg1: PE14<M6>,
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) -> PwmPins {
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let freq = 20u32.khz();
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let channels = (
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max_v0.into_alternate_af2(),
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max_v1.into_alternate_af2(),
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);
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let (max_v0, max_v1) = pwm::tim3(tim3, channels, clocks, freq);
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let channels = (
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max_i_pos0.into_alternate_af1(),
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max_i_pos1.into_alternate_af1(),
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max_i_neg0.into_alternate_af1(),
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max_i_neg1.into_alternate_af1(),
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);
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let (max_i_pos0, max_i_pos1, max_i_neg0, max_i_neg1) =
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pwm::tim1(tim1, channels, clocks, freq);
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PwmPins {
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max_v0, max_v1,
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max_i_pos0, max_i_pos1,
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max_i_neg0, max_i_neg1,
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}
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}
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}
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