From e7782c9cb32ce1ffacddc2855bccba355653bcc8 Mon Sep 17 00:00:00 2001 From: Astro Date: Sat, 21 Mar 2020 00:33:31 +0100 Subject: [PATCH] implement shdn* pins --- src/main.rs | 25 +++++++++++++++++++------ src/pins.rs | 29 ++++++++++++++++++----------- 2 files changed, 37 insertions(+), 17 deletions(-) diff --git a/src/main.rs b/src/main.rs index 9dccd77..1c56376 100644 --- a/src/main.rs +++ b/src/main.rs @@ -16,6 +16,7 @@ use cortex_m_rt::entry; use stm32f4xx_hal::{ hal::{ self, + digital::v2::OutputPin, watchdog::{WatchdogEnable, Watchdog}, }, rcc::RccExt, @@ -100,6 +101,8 @@ fn main() -> ! { let mut dac1 = ad5680::Dac::new(pins.dac1_spi, pins.dac1_sync); dac1.set(0).unwrap(); let mut pwm = pins.pwm; + let mut shdn0 = pins.shdn0; + let mut shdn1 = pins.shdn1; timer::setup(cp.SYST, clocks); @@ -137,10 +140,14 @@ fn main() -> ! { if state.pid_enabled { // Forward PID output to i_set DAC match channel { - 0 => - dac0.set(state.dac_value).unwrap(), - 1 => - dac1.set(state.dac_value).unwrap(), + 0 => { + dac0.set(state.dac_value).unwrap(); + shdn0.set_high().unwrap(); + } + 1 => { + dac1.set(state.dac_value).unwrap(); + shdn1.set_high().unwrap(); + } _ => unreachable!(), } @@ -275,8 +282,14 @@ fn main() -> ! { Command::Pwm { channel, pin: PwmPin::ISet, duty } if duty <= ad5680::MAX_VALUE => { channel_states[channel].pid_enabled = false; match channel { - 0 => dac0.set(duty).unwrap(), - 1 => dac1.set(duty).unwrap(), + 0 => { + dac0.set(duty).unwrap(); + shdn0.set_high().unwrap(); + } + 1 => { + dac1.set(duty).unwrap(); + shdn1.set_high().unwrap(); + } _ => unreachable!(), } channel_states[channel].dac_value = duty; diff --git a/src/pins.rs b/src/pins.rs index c984d8a..0ec039b 100644 --- a/src/pins.rs +++ b/src/pins.rs @@ -1,4 +1,5 @@ use stm32f4xx_hal::{ + hal::digital::v2::OutputPin, gpio::{ AF5, Alternate, gpioa::*, @@ -30,8 +31,10 @@ pub struct Pins { pub pwm: PwmPins, pub dac0_spi: Dac0Spi, pub dac0_sync: PE4>, + pub shdn0: PE10>, pub dac1_spi: Dac1Spi, pub dac1_sync: PF6>, + pub shdn1: PE15>, } impl Pins { @@ -58,15 +61,6 @@ impl Pins { let adc_spi = Self::setup_spi_adc(clocks, spi2, gpiob.pb10, gpiob.pb14, gpiob.pb15); let adc_nss = gpiob.pb12.into_push_pull_output(); - let (dac0_spi, dac0_sync) = Self::setup_dac0( - clocks, spi4, - gpioe.pe2, gpioe.pe4, gpioe.pe6 - ); - let (dac1_spi, dac1_sync) = Self::setup_dac1( - clocks, spi5, - gpiof.pf7, gpiof.pf6, gpiof.pf9 - ); - let pwm = PwmPins::setup( clocks, tim1, tim3, gpioc.pc6, gpioc.pc7, @@ -74,11 +68,24 @@ impl Pins { gpioe.pe13, gpioe.pe14 ); + let (dac0_spi, dac0_sync) = Self::setup_dac0( + clocks, spi4, + gpioe.pe2, gpioe.pe4, gpioe.pe6 + ); + let mut shdn0 = gpioe.pe10.into_push_pull_output(); + let _ = shdn0.set_low(); + let (dac1_spi, dac1_sync) = Self::setup_dac1( + clocks, spi5, + gpiof.pf7, gpiof.pf6, gpiof.pf9 + ); + let mut shdn1 = gpioe.pe15.into_push_pull_output(); + let _ = shdn1.set_low(); + Pins { adc_spi, adc_nss, pwm, - dac0_spi, dac0_sync, - dac1_spi, dac1_sync, + dac0_spi, dac0_sync, shdn0, + dac1_spi, dac1_sync, shdn1, } }