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ad7172: work on adc setup

This commit is contained in:
Astro 2020-03-20 00:45:10 +01:00
parent bb51cce6f6
commit 82dba2bb67
3 changed files with 22 additions and 6 deletions
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14
src/ad7172/adc.rs
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@ -5,7 +5,7 @@ use log::info;
use super::checksum::{ChecksumMode, Checksum}; use super::checksum::{ChecksumMode, Checksum};
use super::AdcError; use super::AdcError;
use super::{ use super::{
regs, regs::RegisterData, regs::{self, Register, RegisterData},
Input, RefSource, PostFilter, DigitalFilterOrder, Input, RefSource, PostFilter, DigitalFilterOrder,
}; };
@ -40,6 +40,10 @@ impl<SPI: Transfer<u8, Error = E>, NSS: OutputPin, E: fmt::Debug> Adc<SPI, NSS>
} }
info!("ADC id: {:04X} ({} retries)", adc_id, retries); info!("ADC id: {:04X} ({} retries)", adc_id, retries);
let mut adc_mode = <regs::AdcMode as Register>::Data::empty();
adc_mode.set_ref_en(true);
adc.write_reg(&regs::AdcMode, &mut adc_mode);
Ok(adc) Ok(adc)
} }
@ -74,16 +78,16 @@ impl<SPI: Transfer<u8, Error = E>, NSS: OutputPin, E: fmt::Debug> Adc<SPI, NSS>
data.set_refbuf_neg(true); data.set_refbuf_neg(true);
data.set_ainbuf_pos(true); data.set_ainbuf_pos(true);
data.set_ainbuf_neg(true); data.set_ainbuf_neg(true);
data.set_ref_sel(RefSource::External); data.set_ref_sel(RefSource::Internal);
})?; })?;
self.update_reg(&regs::FiltCon { index }, |data| { self.update_reg(&regs::FiltCon { index }, |data| {
data.set_enh_filt_en(true); data.set_enh_filt_en(true);
data.set_enh_filt(PostFilter::F16SPS); data.set_enh_filt(PostFilter::F16SPS);
data.set_order(DigitalFilterOrder::Sinc5Sinc1); data.set_order(DigitalFilterOrder::Sinc5Sinc1);
})?; })?;
// let mut offset = <regs::Offset as regs::Register>::Data::empty(); let mut offset = <regs::Offset as regs::Register>::Data::empty();
// offset.set_offset(0); offset.set_offset(0);
// self.write_reg(&regs::Offset { index }, &mut offset); self.write_reg(&regs::Offset { index }, &mut offset);
self.update_reg(&regs::Channel { index }, |data| { self.update_reg(&regs::Channel { index }, |data| {
data.set_setup(index); data.set_setup(index);
data.set_enabled(true); data.set_enabled(true);

12
src/ad7172/regs.rs
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@ -150,7 +150,17 @@ impl status::Data {
reg_bits!(channel, 0, 0..=1, "Channel for which data is ready"); reg_bits!(channel, 0, 0..=1, "Channel for which data is ready");
reg_bit!(adc_error, 0, 6, "ADC error"); reg_bit!(adc_error, 0, 6, "ADC error");
reg_bit!(crc_error, 0, 5, "SPI CRC error"); reg_bit!(crc_error, 0, 5, "SPI CRC error");
reg_bit!(reg_error, 0,4, "Register error"); reg_bit!(reg_error, 0, 4, "Register error");
}
def_reg!(AdcMode, adc_mode, 0x01, 2);
impl adc_mode::Data {
reg_bits!(clockset, set_clocksel, 1, 2..3, "Clock source");
reg_bits!(mode, set_mode, 1, 4..6, "Operating mode");
reg_bits!(delay, set_delay, 0, 0..2, "Delay after channel switch");
reg_bit!(sing_cyc, set_sing_cyc, 1, 5, "Can only used with single channel");
reg_bit!(hide_delay, set_hide_delay, 1, 6, "Hide delay");
reg_bit!(ref_en, set_ref_en, 0, 7, "Enable internal reference, output buffered 2.5 V to REFOUT");
} }
def_reg!(IfMode, if_mode, 0x02, 2); def_reg!(IfMode, if_mode, 0x02, 2);

2
src/main.rs
View File

@ -92,6 +92,8 @@ fn main() -> ! {
); );
let mut adc = ad7172::Adc::new(pins.adc_spi, pins.adc_nss).unwrap(); let mut adc = ad7172::Adc::new(pins.adc_spi, pins.adc_nss).unwrap();
adc.setup_channel(0, ad7172::Input::Ain0, ad7172::Input::Ain1).unwrap();
adc.setup_channel(1, ad7172::Input::Ain2, ad7172::Input::Ain3).unwrap();
let mut dac0 = ad5680::Dac::new(pins.dac0_spi, pins.dac0_sync); let mut dac0 = ad5680::Dac::new(pins.dac0_spi, pins.dac0_sync);
dac0.set(0).unwrap(); dac0.set(0).unwrap();
let mut dac1 = ad5680::Dac::new(pins.dac1_spi, pins.dac1_sync); let mut dac1 = ad5680::Dac::new(pins.dac1_spi, pins.dac1_sync);