add itec_pin

This commit is contained in:
Astro 2020-05-16 23:59:31 +02:00
parent a317eb60fd
commit 7f8dd62a36
4 changed files with 48 additions and 16 deletions

View File

@ -14,8 +14,10 @@ pub struct Channel<C: ChannelPins> {
/// for `i_set` /// for `i_set`
pub dac: ad5680::Dac<C::DacSpi, C::DacSync>, pub dac: ad5680::Dac<C::DacSpi, C::DacSync>,
pub shdn: C::Shdn, pub shdn: C::Shdn,
/// stm32f4 integrated adc
pub adc: C::Adc,
pub itec_pin: C::ItecPin,
/// feedback from `dac` output /// feedback from `dac` output
pub dac_loopback: C::DacLoopback,
pub dac_loopback_pin: C::DacLoopbackPin, pub dac_loopback_pin: C::DacLoopbackPin,
} }
@ -29,7 +31,8 @@ impl<C: ChannelPins> Channel<C> {
state, state,
dac, dac,
shdn: pins.shdn, shdn: pins.shdn,
dac_loopback: pins.dac_loopback, adc: pins.adc,
itec_pin: pins.itec_pin,
dac_loopback_pin: pins.dac_loopback_pin, dac_loopback_pin: pins.dac_loopback_pin,
} }
} }

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@ -84,15 +84,29 @@ impl Channels {
pub fn read_dac_loopback(&mut self, channel: usize) -> u16 { pub fn read_dac_loopback(&mut self, channel: usize) -> u16 {
match channel { match channel {
0 => self.channel0.dac_loopback.convert( 0 => self.channel0.adc.convert(
&self.channel0.dac_loopback_pin, &self.channel0.dac_loopback_pin,
stm32f4xx_hal::adc::config::SampleTime::Cycles_480 stm32f4xx_hal::adc::config::SampleTime::Cycles_480
), ),
1 => self.channel1.dac_loopback.convert( 1 => self.channel1.adc.convert(
&self.channel1.dac_loopback_pin, &self.channel1.dac_loopback_pin,
stm32f4xx_hal::adc::config::SampleTime::Cycles_480 stm32f4xx_hal::adc::config::SampleTime::Cycles_480
), ),
_ => unreachable!(), _ => unreachable!(),
} }
} }
pub fn read_itec(&mut self, channel: usize) -> u16 {
match channel {
0 => self.channel0.adc.convert(
&self.channel0.itec_pin,
stm32f4xx_hal::adc::config::SampleTime::Cycles_480
),
1 => self.channel1.adc.convert(
&self.channel1.itec_pin,
stm32f4xx_hal::adc::config::SampleTime::Cycles_480
),
_ => unreachable!(),
}
}
} }

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@ -142,11 +142,18 @@ fn main() -> ! {
for channel in 0..CHANNELS { for channel in 0..CHANNELS {
if let Some(adc_data) = channels.channel_state(channel).adc_data { if let Some(adc_data) = channels.channel_state(channel).adc_data {
let dac_loopback = channels.read_dac_loopback(channel); let dac_loopback = channels.read_dac_loopback(channel);
let itec = channels.read_itec(channel);
let dcc_u = 5.0;
let itec_u = dcc_u * (itec as f64) / (0xFFF as f64);
let tec_u = (itec_u - 1.5) / 8.0;
let tec_r = 5.0;
let tec_i = tec_u / tec_r;
let state = channels.channel_state(channel); let state = channels.channel_state(channel);
let _ = writeln!( let _ = writeln!(
socket, "t={} raw{}=0x{:06X} dac_loopback=0x{:X}", socket, "t={} raw{}=0x{:06X} dac_loopback=0x{:X} itec=0x{:X} tec={:.2}V/{:.2}A",
state.adc_time, channel, adc_data, state.adc_time, channel, adc_data,
dac_loopback dac_loopback, itec,
tec_u, tec_i,
); );
} }
} }

View File

@ -26,7 +26,8 @@ pub trait ChannelPins {
type DacSpi: Transfer<u8>; type DacSpi: Transfer<u8>;
type DacSync: OutputPin; type DacSync: OutputPin;
type Shdn: OutputPin; type Shdn: OutputPin;
type DacLoopback; type Adc;
type ItecPin;
type DacLoopbackPin; type DacLoopbackPin;
} }
@ -34,7 +35,8 @@ impl ChannelPins for Channel0 {
type DacSpi = Dac0Spi; type DacSpi = Dac0Spi;
type DacSync = PE4<Output<PushPull>>; type DacSync = PE4<Output<PushPull>>;
type Shdn = PE10<Output<PushPull>>; type Shdn = PE10<Output<PushPull>>;
type DacLoopback = Adc<ADC1>; type Adc = Adc<ADC1>;
type ItecPin = PA6<Analog>;
type DacLoopbackPin = PA4<Analog>; type DacLoopbackPin = PA4<Analog>;
} }
@ -42,7 +44,8 @@ impl ChannelPins for Channel1 {
type DacSpi = Dac1Spi; type DacSpi = Dac1Spi;
type DacSync = PF6<Output<PushPull>>; type DacSync = PF6<Output<PushPull>>;
type Shdn = PE15<Output<PushPull>>; type Shdn = PE15<Output<PushPull>>;
type DacLoopback = Adc<ADC2>; type Adc = Adc<ADC2>;
type ItecPin = PB0<Analog>;
type DacLoopbackPin = PA5<Analog>; type DacLoopbackPin = PA5<Analog>;
} }
@ -57,7 +60,8 @@ pub struct ChannelPinSet<C: ChannelPins> {
pub dac_spi: C::DacSpi, pub dac_spi: C::DacSpi,
pub dac_sync: C::DacSync, pub dac_sync: C::DacSync,
pub shdn: C::Shdn, pub shdn: C::Shdn,
pub dac_loopback: C::DacLoopback, pub adc: C::Adc,
pub itec_pin: C::ItecPin,
pub dac_loopback_pin: C::DacLoopbackPin, pub dac_loopback_pin: C::DacLoopbackPin,
} }
@ -106,14 +110,16 @@ impl Pins {
); );
let mut shdn0 = gpioe.pe10.into_push_pull_output(); let mut shdn0 = gpioe.pe10.into_push_pull_output();
let _ = shdn0.set_low(); let _ = shdn0.set_low();
let mut dac_loopback0 = Adc::adc1(adc1, true, Default::default()); let mut adc0 = Adc::adc1(adc1, true, Default::default());
dac_loopback0.enable(); adc0.enable();
let itec0_pin = gpioa.pa6.into_analog();
let dac_loopback0_pin = gpioa.pa4.into_analog(); let dac_loopback0_pin = gpioa.pa4.into_analog();
let channel0 = ChannelPinSet { let channel0 = ChannelPinSet {
dac_spi: dac0_spi, dac_spi: dac0_spi,
dac_sync: dac0_sync, dac_sync: dac0_sync,
shdn: shdn0, shdn: shdn0,
dac_loopback: dac_loopback0, adc: adc0,
itec_pin: itec0_pin,
dac_loopback_pin: dac_loopback0_pin, dac_loopback_pin: dac_loopback0_pin,
}; };
@ -123,14 +129,16 @@ impl Pins {
); );
let mut shdn1 = gpioe.pe15.into_push_pull_output(); let mut shdn1 = gpioe.pe15.into_push_pull_output();
let _ = shdn1.set_low(); let _ = shdn1.set_low();
let mut dac_loopback1 = Adc::adc2(adc2, true, Default::default()); let mut adc1 = Adc::adc2(adc2, true, Default::default());
dac_loopback1.enable(); adc1.enable();
let itec1_pin = gpiob.pb0.into_analog();
let dac_loopback1_pin = gpioa.pa5.into_analog(); let dac_loopback1_pin = gpioa.pa5.into_analog();
let channel1 = ChannelPinSet { let channel1 = ChannelPinSet {
dac_spi: dac1_spi, dac_spi: dac1_spi,
dac_sync: dac1_sync, dac_sync: dac1_sync,
shdn: shdn1, shdn: shdn1,
dac_loopback: dac_loopback1, adc: adc1,
itec_pin: itec1_pin,
dac_loopback_pin: dac_loopback1_pin, dac_loopback_pin: dac_loopback1_pin,
}; };