2024-01-16 15:22:11 +08:00
|
|
|
use core::arch::asm;
|
2021-01-18 16:59:13 +08:00
|
|
|
use cortex_m_rt::pre_init;
|
|
|
|
use stm32f4xx_hal::stm32::{RCC, SYSCFG};
|
|
|
|
|
2021-01-13 11:59:06 +08:00
|
|
|
const DFU_TRIG_MSG: u32 = 0xDECAFBAD;
|
|
|
|
|
|
|
|
extern "C" {
|
|
|
|
// This symbol comes from memory.x
|
|
|
|
static mut _dfu_msg: u32;
|
|
|
|
}
|
|
|
|
|
|
|
|
pub unsafe fn set_dfu_trigger() {
|
|
|
|
_dfu_msg = DFU_TRIG_MSG;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Called by reset handler in lib.rs immediately after reset.
|
|
|
|
/// This function should not be called outside of reset handler as
|
|
|
|
/// bootloader expects MCU to be in reset state when called.
|
2021-01-16 11:04:24 +08:00
|
|
|
#[cfg(target_arch = "arm")]
|
2021-01-13 11:59:06 +08:00
|
|
|
#[pre_init]
|
|
|
|
unsafe fn __pre_init() {
|
|
|
|
if _dfu_msg == DFU_TRIG_MSG {
|
|
|
|
_dfu_msg = 0x00000000;
|
|
|
|
|
|
|
|
// Enable system config controller clock
|
2021-01-18 16:45:01 +08:00
|
|
|
let rcc = &*RCC::ptr();
|
|
|
|
rcc.apb2enr.modify(|_, w| w.syscfgen().set_bit());
|
2021-01-13 11:59:06 +08:00
|
|
|
|
|
|
|
// Bypass BOOT pins and remap bootloader to 0x00000000
|
2021-01-18 16:45:01 +08:00
|
|
|
let syscfg = &*SYSCFG::ptr() ;
|
|
|
|
syscfg.memrm.write(|w| w.mem_mode().bits(0b01));
|
2021-01-13 11:59:06 +08:00
|
|
|
|
2021-01-18 16:45:01 +08:00
|
|
|
// Impose instruction and memory barriers
|
|
|
|
cortex_m::asm::isb();
|
|
|
|
cortex_m::asm::dsb();
|
2021-01-13 11:59:06 +08:00
|
|
|
|
|
|
|
asm!(
|
|
|
|
// Set stack pointer to bootloader location
|
|
|
|
"LDR R0, =0x1FFF0000",
|
|
|
|
"LDR SP,[R0, #0]",
|
|
|
|
// Jump to bootloader
|
|
|
|
"LDR R0,[R0, #4]",
|
|
|
|
"BX R0",
|
|
|
|
);
|
|
|
|
}
|
2021-01-18 16:59:13 +08:00
|
|
|
}
|