forked from M-Labs/nix-scripts
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8 Commits
Author | SHA1 | Date |
---|---|---|
Sébastien Bourdeauducq | 0b8533f9e7 | |
mwojcik | b7c100c2bd | |
mwojcik | b332d72c5e | |
Egor Savkin | c7cafe6e61 | |
Sébastien Bourdeauducq | e9432e25cb | |
Egor Savkin | 3ec9d18b58 | |
Sebastien Bourdeauducq | 938f48d392 | |
mwojcik | 17560a1a1c |
|
@ -16,11 +16,11 @@ let
|
|||
echo file binary-dist $out/urukul.jed >> $out/nix-support/hydra-build-products
|
||||
'';
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};
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buildMirnyCpld = {version, src}: pkgs.stdenv.mkDerivation {
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buildMirnyCpld = {version, patchPhase ? "", src}: pkgs.stdenv.mkDerivation {
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pname = "mirny-cpld";
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inherit src version;
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inherit src version patchPhase;
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buildInputs = [(pkgs.python3.withPackages(ps: [fpgatools.migen]))] ++ (builtins.attrValues fpgatools.ise);
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phases = ["buildPhase" "installPhase"];
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phases = ["unpackPhase" "patchPhase" "buildPhase" "installPhase"];
|
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buildPhase = "python $src/mirny_impl.py";
|
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installPhase =
|
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''
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||||
|
@ -58,14 +58,24 @@ in
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|||
src = <mirnySrc>;
|
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};
|
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mirny-cpld-release = buildMirnyCpld rec {
|
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version = "0.3";
|
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version = "0.3.1";
|
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src = pkgs.fetchFromGitHub {
|
||||
owner = "quartiq";
|
||||
repo = "mirny";
|
||||
rev = "v${version}";
|
||||
sha256 = "sha256-u1iXcbGX6JkVgfpnCbkyTOVoMYnYcSufLBb6OBAeu8c=";
|
||||
sha256 = "sha256-FbPUgXcUByEnczbnDCh8wYPO+rpSZSAabG1rtvA7mIs=";
|
||||
};
|
||||
};
|
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mirny-cpld-legacy-almazny = buildMirnyCpld rec {
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version = "0.2.4";
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src = pkgs.fetchFromGitHub {
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owner = "quartiq";
|
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repo = "mirny";
|
||||
rev = "v${version}";
|
||||
sha256 = "sha256-/O1AE0JOXALC8I7NPhOd8h18oX8Qu7lj+6ToAMMD3zs=";
|
||||
};
|
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patchPhase = "patch -p1 < ${./mirny-legacy-almazny.diff}";
|
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};
|
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fastino-fpga = pkgs.stdenv.mkDerivation {
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name = "fastino-fpga";
|
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src = <fastinoSrc>;
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|
|
|
@ -1,4 +1,4 @@
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{ pkgs, isePath ? "/opt/Xilinx/14.7/ISE_DS", vivadoPath ? "/opt/Xilinx/Vivado/2021.2" }:
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{ pkgs, isePath ? "/opt/Xilinx/14.7/ISE_DS", vivadoPath ? "/opt/Xilinx/Vivado/2022.2" }:
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rec {
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ise = let
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makeXilinxEnv = name: pkgs.buildFHSUserEnv {
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|
|
|
@ -0,0 +1,313 @@
|
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diff --git a/Makefile b/Makefile
|
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index 667b8e7..ed97303 100644
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--- a/Makefile
|
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+++ b/Makefile
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@@ -8,9 +8,15 @@ test:
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.PHONY: build
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build: build/mirny.vm6
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|
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+.PHONY: legacy_almazny
|
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+legacy_almazny: build/mirny_legacy_almazny.vm6
|
||||
+
|
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build/mirny.vm6: mirny.py mirny_cpld.py
|
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python mirny_impl.py
|
||||
|
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+build/mirny_legacy_almazny.vm6: mirny.py mirny_cpld.py
|
||||
+ python mirny_impl.py --legacy-almazny
|
||||
+
|
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REV:=$(shell git describe --always --abbrev=8 --dirty)
|
||||
|
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.PHONY: release
|
||||
diff --git a/README.md b/README.md
|
||||
index 1bea35a..5e93809 100644
|
||||
--- a/README.md
|
||||
+++ b/README.md
|
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@@ -1,23 +1,39 @@
|
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-# Mirny CPLD code
|
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+# Mirny CPLD gateware
|
||||
|
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-[Mirny overview](https://github.com/sinara-hw/mirny/wiki)
|
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+## Hardware
|
||||
+
|
||||
+[![Hardware](https://github.com/sinara-hw/mirny/wiki/Mirny_v1.0_top_small.jpg)](https://github.com/sinara-hw/mirny/wiki)
|
||||
|
||||
[Mirny Schematics](https://github.com/sinara-hw/mirny/releases)
|
||||
|
||||
## Building
|
||||
|
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-Needs migen and ISE.
|
||||
+Needs [migen](https://github.com/m-labs/migen) and [Xilinx ISE](https://www.xilinx.com/products/design-tools/ise-design-suite.html). Assumes ISE is installed in ``/opt/Xilinx``.
|
||||
|
||||
```
|
||||
make
|
||||
-# and then look at/use flash.sh or make flash
|
||||
-
|
||||
-# or use fxload and xc3sprog:
|
||||
-/sbin/fxload -t fx2 -I /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xusb_xp2.hex -D /dev/bus/usb/001/*`cat /sys/bus/usb/devices/1-3/devnum` && sleep 10 && \
|
||||
-xc3sprog -c xpc -m /opt/Xilinx/14.7/ISE_DS/ISE/xbr/data -v build/mirny.jed:w
|
||||
-# look for "Verify: Success"
|
||||
```
|
||||
|
||||
+## Flashing
|
||||
+
|
||||
+With Digilent [JTAG HS2](https://store.digilentinc.com/jtag-hs2-programming-cable/) cable:
|
||||
+
|
||||
+ - download firmware to dongle. Manually (adjust USB bus as needed):
|
||||
+ ```
|
||||
+ /sbin/fxload -t fx2 -I /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xusb_xp2.hex -D /dev/bus/usb/001/*`cat /sys/bus/usb/devices/1-3/devnum`
|
||||
+ ```
|
||||
+ or automatically via the ``udev`` rule:
|
||||
+ ```
|
||||
+ SUBSYSTEM=="usb", ACTION="add", ATTR{idVendor}=="0403", ATTR{idProduct}=="6014", ATTR{manufacturer}=="Digilent", RUN+="/usr/bin/fxload -v -t fx2 -I /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xusb_xp2.hex -D $tempnode"
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+ ```
|
||||
+
|
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+ - install [xc3sprog](http://xc3sprog.sourceforge.net/)
|
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+
|
||||
+ - ``flash_xc3.sh jtaghs2``
|
||||
+
|
||||
+ - look for ``Verify: Success``
|
||||
+
|
||||
+
|
||||
# License
|
||||
|
||||
GPLv3+
|
||||
diff --git a/flash_xc3.sh b/flash_xc3.sh
|
||||
index 4c8a94c..c84b4d6 100755
|
||||
--- a/flash_xc3.sh
|
||||
+++ b/flash_xc3.sh
|
||||
@@ -1,8 +1,9 @@
|
||||
#!/bin/bash
|
||||
|
||||
set -e
|
||||
-set -x
|
||||
|
||||
-/sbin/fxload -t fx2 -I /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xusb_xp2.hex -D /dev/bus/usb/001/*`cat /sys/bus/usb/devices/1-7/devnum`
|
||||
-sleep 7
|
||||
-../xc3sprog/build/xc3sprog -c xpc -m /opt/Xilinx/14.7/ISE_DS/ISE/xbr/data -v build/mirny.jed:w
|
||||
+XC3SPROG=xc3sprog
|
||||
+CABLE=${1-xpc}
|
||||
+
|
||||
+set -x
|
||||
+$XC3SPROG -c $CABLE -m /opt/Xilinx/14.7/ISE_DS/ISE/xbr/data -v build/mirny.jed:w
|
||||
diff --git a/mirny.py b/mirny.py
|
||||
index 82edca2..6dc2612 100644
|
||||
--- a/mirny.py
|
||||
+++ b/mirny.py
|
||||
@@ -153,7 +153,6 @@ class SR(Module):
|
||||
),
|
||||
]
|
||||
|
||||
-
|
||||
def intersection(a, b):
|
||||
(aa, am), (ba, bm) = a, b
|
||||
# TODO
|
||||
@@ -182,26 +181,26 @@ class Mirny(Module):
|
||||
SPI
|
||||
---
|
||||
|
||||
- SPI xfer is ADR(7), WE(1), DAT(REG: 16, ATT: 8, PLL: 32)
|
||||
-
|
||||
- | ADR | TARGET |
|
||||
- |--------+--------|
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- | 0 | REG0 |
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- | 1 | REG1 |
|
||||
- | 2 | REG2 |
|
||||
- | 3 | REG3 |
|
||||
- | 4 | PLL0 |
|
||||
- | 5 | PLL1 |
|
||||
- | 6 | PLL2 |
|
||||
- | 7 | PLL3 |
|
||||
- | 8 | ATT0 |
|
||||
- | 9 | ATT1 |
|
||||
- | a | ATT2 |
|
||||
- | b | ATT3 |
|
||||
- | c | reserved |
|
||||
- | d | reserved |
|
||||
- | e | reserved |
|
||||
- | f | reserved |
|
||||
+ SPI xfer is ADR(7), WE(1), DAT(REG: 16, ATT: 8, PLL: 32, SR: 8)
|
||||
+
|
||||
+ | ADR | TARGET |
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||||
+ |-----+----------------------|
|
||||
+ | 0 | REG0 |
|
||||
+ | 1 | REG1 |
|
||||
+ | 2 | REG2 |
|
||||
+ | 3 | REG3 |
|
||||
+ | 4 | PLL0 |
|
||||
+ | 5 | PLL1 |
|
||||
+ | 6 | PLL2 |
|
||||
+ | 7 | PLL3 |
|
||||
+ | 8 | ATT0 |
|
||||
+ | 9 | ATT1 |
|
||||
+ | a | ATT2 |
|
||||
+ | b | ATT3 |
|
||||
+ | c | (Legacy Almazny) SR1 |
|
||||
+ | d | (Legacy Almazny) SR2 |
|
||||
+ | e | (Legacy Almazny) SR3 |
|
||||
+ | f | (Legacy Almazny) SR4 |
|
||||
|
||||
The SPI interface is CPOL=0, CPHA=0, SPI mode 0, 4-wire, full fuplex.
|
||||
|
||||
@@ -223,8 +222,8 @@ class Mirny(Module):
|
||||
| Name | Width | Function |
|
||||
|-----------+-------+------------------------------------|
|
||||
| CE_N | 4 | PLL chip enable (bar) |
|
||||
- | CLK_SEL | 2 | Selects CLK source: 0 OSC, 1 MMCX, |
|
||||
- | | | 2 reserved, 3 SMA |
|
||||
+ | CLK_SEL | 2 | Selects CLK source: |
|
||||
+ | | | 0 OSC, 1 reserved, 2 MMCX, 3 SMA |
|
||||
| DIV | 2 | Clock divider configuration: |
|
||||
| | | 0: divide-by-one, |
|
||||
| | | 1: reserved, |
|
||||
@@ -234,6 +233,7 @@ class Mirny(Module):
|
||||
| FSEN_N | 1 | LVDS fail safe, Type 2 (bar) |
|
||||
| MUXOUT_EEM| 1 | route MUXOUT to EEM[4:8] |
|
||||
| EEM_MEZZIO| 1 | route EEM[4:8] to MEZZ_IO[0:4] |
|
||||
+ | ALMAZNY_OE| 1 | Almazny OE in legacy Almazny mode |
|
||||
|
||||
| Name | Width | Function |
|
||||
|-----------+-------+------------------------------------|
|
||||
@@ -250,7 +250,7 @@ class Mirny(Module):
|
||||
The test points expose miscellaneous signals for debugging and are not part
|
||||
of the protocol revision.
|
||||
"""
|
||||
- def __init__(self, platform):
|
||||
+ def __init__(self, platform, legacy_almazny=False):
|
||||
self.eem = eem = []
|
||||
for i in range(8):
|
||||
tsi = TSTriple()
|
||||
@@ -292,7 +292,7 @@ class Mirny(Module):
|
||||
self.sr.ext.cs.eq(eem[3].i),
|
||||
]
|
||||
|
||||
- regs = [REG(), REG(width=12), REG(width=4), REG()]
|
||||
+ regs = [REG(), REG(width=13), REG(width=4), REG()]
|
||||
self.submodules += regs
|
||||
for i, reg in enumerate(regs):
|
||||
self.sr.connect(reg.bus, adr=i, mask=mask)
|
||||
@@ -310,23 +310,47 @@ class Mirny(Module):
|
||||
clk = platform.request("clk")
|
||||
clk_div = TSTriple()
|
||||
self.specials += clk_div.get_tristate(clk.div)
|
||||
- # in_sel: 00: XO, 01: MMCX, 10: n/a (SMA+XO), 11: SMA
|
||||
+ # in_sel: 00: XO, 01: n/a (SMA+XO), 10: MMCX, 11: SMA
|
||||
# dividers: 00(z): 1, 01(z): 1, 10(low): 2, 11(high) 4
|
||||
self.comb += [
|
||||
Cat(clk.in_sel, clk_div.o, clk_div.oe).eq(regs[1].write[4:8]),
|
||||
platform.request("fsen").eq(~regs[1].write[9]),
|
||||
]
|
||||
|
||||
- for i, m in enumerate(platform.request("mezz_io")):
|
||||
- tsi = TSTriple()
|
||||
- self.specials += tsi.get_tristate(m)
|
||||
+ if legacy_almazny:
|
||||
+ almazny_io = platform.request("legacy_almazny_common")
|
||||
+ almazny_adr = 0b1100 # 1100 - and then 1101, 1110, 1111 for sr 1-4
|
||||
+ ext = Record(ext_layout)
|
||||
+ self.sr.connect_ext(ext, almazny_adr, almazny_adr)
|
||||
+ latches = AsyncRst(width=4, reset=0xF)
|
||||
+ self.submodules += latches
|
||||
+
|
||||
self.comb += [
|
||||
- tsi.o.eq(regs[3].write[i] | (0 if i >= 4 else
|
||||
- (regs[1].write[11] & eem[i + 4].i))),
|
||||
- regs[3].read[i].eq(tsi.i),
|
||||
- tsi.oe.eq(regs[3].write[i + 8]),
|
||||
- regs[3].read[i + 8].eq(tsi.oe),
|
||||
+ latches.ce.eq(ext.cs),
|
||||
+ almazny_io.clk.eq(ext.sck),
|
||||
+ almazny_io.mosi.eq(ext.sdi),
|
||||
+ almazny_io.srclr.eq(1)
|
||||
]
|
||||
+
|
||||
+ for i in range(4):
|
||||
+ almazny = platform.request("legacy_almazny", i)
|
||||
+ self.sync += latches.i[i].eq(self.sr.bus.adr[:2] != i)
|
||||
+ self.comb += [
|
||||
+ almazny.latch.eq(latches.o[i]),
|
||||
+ almazny.noe.eq(~regs[1].write[12])
|
||||
+ ]
|
||||
+
|
||||
+ else:
|
||||
+ for i, m in enumerate(platform.request("mezz_io")):
|
||||
+ tsi = TSTriple()
|
||||
+ self.specials += tsi.get_tristate(m)
|
||||
+ self.comb += [
|
||||
+ tsi.o.eq(regs[3].write[i] | (0 if i >= 4 else
|
||||
+ (regs[1].write[11] & eem[i + 4].i))),
|
||||
+ regs[3].read[i].eq(tsi.i),
|
||||
+ tsi.oe.eq(regs[3].write[i + 8]),
|
||||
+ regs[3].read[i + 8].eq(tsi.oe),
|
||||
+ ]
|
||||
|
||||
for i in range(4):
|
||||
rf_sw = platform.request("rf_sw", i)
|
||||
diff --git a/mirny_cpld.py b/mirny_cpld.py
|
||||
index 70fc164..a688d89 100644
|
||||
--- a/mirny_cpld.py
|
||||
+++ b/mirny_cpld.py
|
||||
@@ -16,9 +16,33 @@ _io = [
|
||||
# fail save LVDS enable, LVDS mode selection
|
||||
# high: type 2 receiver, failsafe low
|
||||
("fsen", 0, Pins("P80")),
|
||||
-
|
||||
+
|
||||
+ # IO from 0 to 7
|
||||
("mezz_io", 0, Pins("P57 P58 P59 P60 P61 P64 P68 P69")),
|
||||
|
||||
+ # legacy (v1.0-1.1) Almazny pins
|
||||
+ ("legacy_almazny_common", 0,
|
||||
+ Subsignal("mosi", Pins("P94")),
|
||||
+ Subsignal("clk", Pins("P97")),
|
||||
+ Subsignal("srclr", Pins("P60")),
|
||||
+ ),
|
||||
+ ("legacy_almazny", 0,
|
||||
+ Subsignal("latch", Pins("P96")),
|
||||
+ Subsignal("noe", Pins("P95")),
|
||||
+ ),
|
||||
+ ("legacy_almazny", 1,
|
||||
+ Subsignal("latch", Pins("P100")),
|
||||
+ Subsignal("noe", Pins("P98")),
|
||||
+ ),
|
||||
+ ("legacy_almazny", 2,
|
||||
+ Subsignal("latch", Pins("P92")),
|
||||
+ Subsignal("noe", Pins("P101")),
|
||||
+ ),
|
||||
+ ("legacy_almazny", 3,
|
||||
+ Subsignal("latch", Pins("P57")),
|
||||
+ Subsignal("noe", Pins("P58")),
|
||||
+ ),
|
||||
+
|
||||
("clk", 0,
|
||||
Subsignal("div", Pins("P53")),
|
||||
Subsignal("in_sel", Pins("P54 P56")),
|
||||
diff --git a/mirny_impl.py b/mirny_impl.py
|
||||
index 0c42b0b..d7022dc 100644
|
||||
--- a/mirny_impl.py
|
||||
+++ b/mirny_impl.py
|
||||
@@ -1,10 +1,23 @@
|
||||
+import argparse
|
||||
+
|
||||
+def get_argparser():
|
||||
+ parser = argparse.ArgumentParser(
|
||||
+ description="Mirny CPLD firmware"
|
||||
+ )
|
||||
+ parser.add_argument("--legacy-almazny", action="store_true", default=False)
|
||||
+
|
||||
+ return parser
|
||||
+
|
||||
def main():
|
||||
from mirny_cpld import Platform
|
||||
from mirny import Mirny
|
||||
|
||||
+ args = get_argparser().parse_args()
|
||||
+
|
||||
p = Platform()
|
||||
- mirny = Mirny(p)
|
||||
- p.build(mirny, build_name="mirny", mode="cpld")
|
||||
+ mirny = Mirny(p, args.legacy_almazny)
|
||||
+ build_name = "mirny" if not args.legacy_almazny else "mirny_legacy_almazny"
|
||||
+ p.build(mirny, build_name=build_name, mode="cpld")
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
|
@ -8,8 +8,8 @@ let
|
|||
"thumbv7em-none-eabihf"
|
||||
];
|
||||
rustManifest = pkgs.fetchurl {
|
||||
url = "https://static.rust-lang.org/dist/2023-12-07/channel-rust-stable.toml";
|
||||
sha256 = "sha256-PjvuouwTsYfNKW5Vi5Ye7y+lL7SsWGBxCtBOOm2z14c=";
|
||||
url = "https://static.rust-lang.org/dist/2024-06-13/channel-rust-stable.toml";
|
||||
sha256 = "sha256-Ngiz76YP4HTY75GGdH2P+APE/DEIx2R/Dn+BwwOyzZU=";
|
||||
};
|
||||
rustChannelOfTargets = _channel: _date: targets:
|
||||
(pkgs.lib.rustLib.fromManifestFile rustManifest {
|
||||
|
@ -24,12 +24,12 @@ let
|
|||
cargo = rust;
|
||||
});
|
||||
|
||||
buildStm32Firmware = { name, src, cargoDepsName ? name, cargoPatches ? [], patchPhase ? "", extraNativeBuildInputs ? [], checkPhase ? "", doCheck ? true, binaryName ? name, extraCargoBuildArgs ? "", outputHashes ? {} }:
|
||||
buildStm32Firmware = { name, src, cargoDepsName ? name, patchPhase ? "", extraNativeBuildInputs ? [], checkPhase ? "", doCheck ? true, binaryName ? name, extraCargoBuildArgs ? "", outputHashes ? {} }:
|
||||
rustPlatform.buildRustPackage rec {
|
||||
inherit name cargoDepsName;
|
||||
version = "0.0.0";
|
||||
|
||||
inherit src cargoPatches;
|
||||
inherit src;
|
||||
|
||||
cargoLock = { lockFile = "${src}/Cargo.lock"; inherit outputHashes; };
|
||||
|
||||
|
@ -66,10 +66,10 @@ in
|
|||
patchPhase = ''
|
||||
patch -p1 < ${./pounder-725.diff}
|
||||
'';
|
||||
cargoPatches = [
|
||||
./pounder-cargo-patch.diff
|
||||
];
|
||||
doCheck = false;
|
||||
outputHashes = {
|
||||
"menu-0.6.0" = "sha256-Zilj27J4a/T/Je2qJr6igFj2OEw0/4fU4f0t+afm4TY=";
|
||||
};
|
||||
} // value))) {
|
||||
dual-iir = {};
|
||||
dual-iir-pounder_v1_0 = {
|
||||
|
|
|
@ -216,9 +216,18 @@ index 025f7d4f..59578cce 100644
|
|||
fn add_write(&mut self, register: Register, value: &[u8]) {
|
||||
let data = &mut self.data[self.index..];
|
||||
diff --git a/src/bin/dual-iir.rs b/src/bin/dual-iir.rs
|
||||
index a4a04be8..83dcdefb 100644
|
||||
index ea566e14..84bde34a 100644
|
||||
--- a/src/bin/dual-iir.rs
|
||||
+++ b/src/bin/dual-iir.rs
|
||||
@@ -28,7 +28,7 @@
|
||||
#![no_std]
|
||||
#![no_main]
|
||||
|
||||
-use core::mem::MaybeUninit;
|
||||
+use core::mem::{MaybeUninit, size_of};
|
||||
use core::sync::atomic::{fence, Ordering};
|
||||
use serde::{Deserialize, Serialize};
|
||||
|
||||
@@ -47,6 +47,8 @@ use stabilizer::{
|
||||
dac::{Dac0Output, Dac1Output, DacCode},
|
||||
hal,
|
||||
|
@ -231,7 +240,7 @@ index a4a04be8..83dcdefb 100644
|
|||
@@ -179,6 +181,16 @@ pub struct DualIir {
|
||||
/// See [signal_generator::BasicConfig#miniconf]
|
||||
#[tree(depth = 2)]
|
||||
signal_generator: [signal_generator::BasicConfig; 2],
|
||||
source: [signal_generator::BasicConfig; 2],
|
||||
+
|
||||
+ /// Specifies the config for pounder DDS clock configuration, DDS channels & attenuations
|
||||
+ ///
|
||||
|
@ -246,9 +255,9 @@ index a4a04be8..83dcdefb 100644
|
|||
|
||||
impl Default for DualIir {
|
||||
@@ -206,6 +218,8 @@ impl Default for DualIir {
|
||||
signal_generator: [signal_generator::BasicConfig::default(); 2],
|
||||
source: Default::default(),
|
||||
|
||||
stream_target: StreamTarget::default(),
|
||||
stream: Default::default(),
|
||||
+
|
||||
+ pounder: None.into(),
|
||||
}
|
||||
|
@ -257,7 +266,7 @@ index a4a04be8..83dcdefb 100644
|
|||
@@ -222,6 +236,7 @@ mod app {
|
||||
active_settings: DualIir,
|
||||
telemetry: TelemetryBuffer,
|
||||
signal_generator: [SignalGenerator; 2],
|
||||
source: [SignalGenerator; 2],
|
||||
+ pounder: Option<Pounder>,
|
||||
}
|
||||
|
||||
|
@ -313,12 +322,12 @@ index a4a04be8..83dcdefb 100644
|
|||
}
|
||||
}
|
||||
|
||||
- #[task(priority = 1, local=[afes], shared=[network, settings, active_settings, signal_generator])]
|
||||
+ #[task(priority = 1, local=[afes, dds_clock_state], shared=[network, settings, active_settings, signal_generator, pounder])]
|
||||
- #[task(priority = 1, local=[afes], shared=[network, settings, active_settings, source])]
|
||||
+ #[task(priority = 1, local=[afes, dds_clock_state], shared=[network, settings, active_settings, source, pounder])]
|
||||
async fn settings_update(mut c: settings_update::Context) {
|
||||
c.shared.settings.lock(|settings| {
|
||||
c.local.afes.0.set_gain(settings.dual_iir.afe[0]);
|
||||
@@ -482,6 +507,17 @@ mod app {
|
||||
@@ -480,6 +505,17 @@ mod app {
|
||||
),
|
||||
}
|
||||
}
|
||||
|
@ -334,9 +343,9 @@ index a4a04be8..83dcdefb 100644
|
|||
+ }
|
||||
+ });
|
||||
|
||||
let target = settings.dual_iir.stream_target.into();
|
||||
c.shared.network.lock(|net| net.direct_stream(target));
|
||||
@@ -492,22 +528,31 @@ mod app {
|
||||
c.shared
|
||||
.network
|
||||
@@ -491,21 +527,30 @@ mod app {
|
||||
});
|
||||
}
|
||||
|
||||
|
@ -344,8 +353,7 @@ index a4a04be8..83dcdefb 100644
|
|||
+ #[task(priority = 1, shared=[network, settings, telemetry, pounder], local=[cpu_temp_sensor])]
|
||||
async fn telemetry(mut c: telemetry::Context) {
|
||||
loop {
|
||||
let telemetry: TelemetryBuffer =
|
||||
c.shared.telemetry.lock(|telemetry| *telemetry);
|
||||
let telemetry = c.shared.telemetry.lock(|telemetry| *telemetry);
|
||||
|
||||
- let (gains, telemetry_period) =
|
||||
+ let (gains, telemetry_period, pounder_config) =
|
||||
|
@ -372,10 +380,19 @@ index a4a04be8..83dcdefb 100644
|
|||
});
|
||||
|
||||
diff --git a/src/bin/lockin.rs b/src/bin/lockin.rs
|
||||
index e0cfb58f..c9b26831 100644
|
||||
index 3ddecd7c..77a7474b 100644
|
||||
--- a/src/bin/lockin.rs
|
||||
+++ b/src/bin/lockin.rs
|
||||
@@ -551,6 +551,7 @@ mod app {
|
||||
@@ -29,7 +29,7 @@
|
||||
|
||||
use core::{
|
||||
convert::TryFrom,
|
||||
- mem::MaybeUninit,
|
||||
+ mem::{MaybeUninit, size_of},
|
||||
sync::atomic::{fence, Ordering},
|
||||
};
|
||||
|
||||
@@ -547,6 +547,7 @@ mod app {
|
||||
gains[0],
|
||||
gains[1],
|
||||
c.local.cpu_temp_sensor.get_temperature().unwrap(),
|
||||
|
@ -691,11 +708,24 @@ index 5bc7e9ff..5b8d5d30 100644
|
|||
+ }
|
||||
+ }
|
||||
+}
|
||||
diff --git a/src/net/data_stream.rs b/src/net/data_stream.rs
|
||||
index 714ec57f..d442f197 100644
|
||||
--- a/src/net/data_stream.rs
|
||||
+++ b/src/net/data_stream.rs
|
||||
@@ -25,7 +25,7 @@
|
||||
|
||||
#![allow(non_camel_case_types)] // https://github.com/rust-embedded/heapless/issues/411
|
||||
|
||||
-use core::{fmt::Write, mem::MaybeUninit};
|
||||
+use core::{fmt::Write, mem::{MaybeUninit, size_of_val}};
|
||||
use heapless::{
|
||||
box_pool,
|
||||
pool::boxed::{Box, BoxBlock},
|
||||
diff --git a/src/net/mod.rs b/src/net/mod.rs
|
||||
index a10b7cdb..efa2b8c8 100644
|
||||
index 43733fa8..a8b90f86 100644
|
||||
--- a/src/net/mod.rs
|
||||
+++ b/src/net/mod.rs
|
||||
@@ -33,14 +33,14 @@ pub type NetworkReference =
|
||||
@@ -32,14 +32,14 @@ pub type NetworkReference =
|
||||
|
||||
pub struct MqttStorage {
|
||||
telemetry: [u8; 2048],
|
||||
|
@ -713,7 +743,7 @@ index a10b7cdb..efa2b8c8 100644
|
|||
}
|
||||
}
|
||||
diff --git a/src/net/telemetry.rs b/src/net/telemetry.rs
|
||||
index 4aa82601..3dc3086c 100644
|
||||
index c8eb536b..116382a3 100644
|
||||
--- a/src/net/telemetry.rs
|
||||
+++ b/src/net/telemetry.rs
|
||||
@@ -16,7 +16,7 @@ use minimq::{DeferredPublication, Publication};
|
||||
|
|
|
@ -1,28 +0,0 @@
|
|||
diff --git a/Cargo.lock b/Cargo.lock
|
||||
index 7c796acf..cee5ba60 100644
|
||||
--- a/Cargo.lock
|
||||
+++ b/Cargo.lock
|
||||
@@ -983,9 +983,9 @@ dependencies = [
|
||||
|
||||
[[package]]
|
||||
name = "serde"
|
||||
-version = "1.0.203"
|
||||
+version = "1.0.202"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
-checksum = "7253ab4de971e72fb7be983802300c30b5a7f0c2e56fab8abfc6a214307c0094"
|
||||
+checksum = "226b61a0d411b2ba5ff6d7f73a476ac4f8bb900373459cd00fab8512828ba395"
|
||||
dependencies = [
|
||||
"serde_derive",
|
||||
]
|
||||
@@ -1003,9 +1003,9 @@ dependencies = [
|
||||
|
||||
[[package]]
|
||||
name = "serde_derive"
|
||||
-version = "1.0.203"
|
||||
+version = "1.0.202"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
-checksum = "500cbc0ebeb6f46627f50f3f5811ccf6bf00643be300b4c3eabc0ef55dc5b5ba"
|
||||
+checksum = "6048858004bcff69094cd972ed40a32500f153bd3be9f716b2eed2e8217c4838"
|
||||
dependencies = [
|
||||
"proc-macro2",
|
||||
"quote",
|
5
web.nix
5
web.nix
|
@ -5,6 +5,11 @@ let
|
|||
in
|
||||
rec {
|
||||
web = pkgs.runCommand "web" {} "cd ${web-src}; ${pkgs.zola}/bin/zola build -o $out";
|
||||
web-intl = pkgs.runCommand "web-intl" {}
|
||||
''
|
||||
cd ${web-src}
|
||||
DOMAINNAME=m-labs-intl.com ${pkgs.zola}/bin/zola build -o $out
|
||||
'';
|
||||
sphinxcontrib-platformpicker = pkgs.python3Packages.buildPythonPackage rec {
|
||||
pname = "sphinxcontrib-platformpicker";
|
||||
version = "1.3";
|
||||
|
|
Loading…
Reference in New Issue