forked from M-Labs/artiq-zynq
590 lines
18 KiB
Rust
590 lines
18 KiB
Rust
use core_io::{Error as IoError, Read, Write};
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use io::proto::{ProtoRead, ProtoWrite};
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/* 512 (max size) - 4 (CRC) - 1 (packet ID) - 1 (destination) - 4 (trace ID) - 1 (last) - 2 (length) */
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pub const DMA_TRACE_MAX_SIZE: usize = 499;
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#[derive(Debug)]
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pub enum Error {
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UnknownPacket(u8),
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Io(IoError),
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}
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impl From<IoError> for Error {
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fn from(value: IoError) -> Error {
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Error::Io(value)
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}
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}
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#[derive(PartialEq, Debug)]
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pub enum Packet {
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EchoRequest,
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EchoReply,
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ResetRequest,
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ResetAck,
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TSCAck,
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DestinationStatusRequest {
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destination: u8,
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},
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DestinationDownReply,
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DestinationOkReply,
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DestinationSequenceErrorReply {
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channel: u16,
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},
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DestinationCollisionReply {
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channel: u16,
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},
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DestinationBusyReply {
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channel: u16,
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},
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RoutingSetPath {
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destination: u8,
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hops: [u8; 32],
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},
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RoutingSetRank {
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rank: u8,
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},
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RoutingAck,
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MonitorRequest {
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destination: u8,
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channel: u16,
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probe: u8,
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},
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MonitorReply {
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value: u64,
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},
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InjectionRequest {
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destination: u8,
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channel: u16,
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overrd: u8,
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value: u8,
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},
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InjectionStatusRequest {
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destination: u8,
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channel: u16,
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overrd: u8,
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},
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InjectionStatusReply {
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value: u8,
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},
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I2cStartRequest {
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destination: u8,
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busno: u8,
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},
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I2cRestartRequest {
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destination: u8,
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busno: u8,
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},
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I2cStopRequest {
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destination: u8,
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busno: u8,
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},
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I2cWriteRequest {
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destination: u8,
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busno: u8,
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data: u8,
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},
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I2cWriteReply {
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succeeded: bool,
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ack: bool,
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},
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I2cReadRequest {
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destination: u8,
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busno: u8,
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ack: bool,
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},
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I2cReadReply {
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succeeded: bool,
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data: u8,
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},
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I2cBasicReply {
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succeeded: bool,
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},
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I2cSwitchSelectRequest {
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destination: u8,
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busno: u8,
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address: u8,
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mask: u8,
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},
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SpiSetConfigRequest {
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destination: u8,
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busno: u8,
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flags: u8,
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length: u8,
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div: u8,
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cs: u8,
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},
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SpiWriteRequest {
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destination: u8,
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busno: u8,
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data: u32,
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},
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SpiReadRequest {
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destination: u8,
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busno: u8,
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},
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SpiReadReply {
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succeeded: bool,
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data: u32,
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},
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SpiBasicReply {
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succeeded: bool,
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},
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DmaAddTraceRequest {
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destination: u8,
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id: u32,
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last: bool,
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length: u16,
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trace: [u8; DMA_TRACE_MAX_SIZE]
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},
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DmaAddTraceReply {
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succeeded: bool
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},
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DmaRemoveTraceRequest {
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destination: u8,
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id: u32
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},
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DmaRemoveTraceReply {
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succeeded: bool
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},
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DmaPlaybackRequest {
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destination: u8,
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id: u32,
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timestamp: u64
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},
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DmaPlaybackReply {
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succeeded: bool
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},
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DmaPlaybackStatus {
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destination: u8,
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id: u32,
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error: u8,
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channel: u32,
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timestamp: u64
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},
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}
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impl Packet {
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pub fn read_from<R>(reader: &mut R) -> Result<Self, Error>
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where R: Read + ?Sized {
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Ok(match reader.read_u8()? {
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0x00 => Packet::EchoRequest,
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0x01 => Packet::EchoReply,
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0x02 => Packet::ResetRequest,
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0x03 => Packet::ResetAck,
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0x04 => Packet::TSCAck,
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0x20 => Packet::DestinationStatusRequest {
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destination: reader.read_u8()?,
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},
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0x21 => Packet::DestinationDownReply,
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0x22 => Packet::DestinationOkReply,
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0x23 => Packet::DestinationSequenceErrorReply {
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channel: reader.read_u16()?,
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},
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0x24 => Packet::DestinationCollisionReply {
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channel: reader.read_u16()?,
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},
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0x25 => Packet::DestinationBusyReply {
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channel: reader.read_u16()?,
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},
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0x30 => {
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let destination = reader.read_u8()?;
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let mut hops = [0; 32];
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reader.read_exact(&mut hops)?;
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Packet::RoutingSetPath {
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destination: destination,
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hops: hops,
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}
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}
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0x31 => Packet::RoutingSetRank {
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rank: reader.read_u8()?,
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},
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0x32 => Packet::RoutingAck,
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0x40 => Packet::MonitorRequest {
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destination: reader.read_u8()?,
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channel: reader.read_u16()?,
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probe: reader.read_u8()?,
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},
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0x41 => Packet::MonitorReply {
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value: reader.read_u64()?,
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},
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0x50 => Packet::InjectionRequest {
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destination: reader.read_u8()?,
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channel: reader.read_u16()?,
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overrd: reader.read_u8()?,
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value: reader.read_u8()?,
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},
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0x51 => Packet::InjectionStatusRequest {
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destination: reader.read_u8()?,
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channel: reader.read_u16()?,
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overrd: reader.read_u8()?,
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},
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0x52 => Packet::InjectionStatusReply {
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value: reader.read_u8()?,
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},
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0x80 => Packet::I2cStartRequest {
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destination: reader.read_u8()?,
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busno: reader.read_u8()?,
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},
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0x81 => Packet::I2cRestartRequest {
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destination: reader.read_u8()?,
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busno: reader.read_u8()?,
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},
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0x82 => Packet::I2cStopRequest {
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destination: reader.read_u8()?,
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busno: reader.read_u8()?,
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},
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0x83 => Packet::I2cWriteRequest {
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destination: reader.read_u8()?,
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busno: reader.read_u8()?,
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data: reader.read_u8()?,
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},
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0x84 => Packet::I2cWriteReply {
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succeeded: reader.read_bool()?,
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ack: reader.read_bool()?,
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},
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0x85 => Packet::I2cReadRequest {
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destination: reader.read_u8()?,
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busno: reader.read_u8()?,
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ack: reader.read_bool()?,
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},
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0x86 => Packet::I2cReadReply {
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succeeded: reader.read_bool()?,
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data: reader.read_u8()?,
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},
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0x87 => Packet::I2cBasicReply {
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succeeded: reader.read_bool()?,
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},
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0x88 => Packet::I2cSwitchSelectRequest {
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destination: reader.read_u8()?,
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busno: reader.read_u8()?,
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address: reader.read_u8()?,
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mask: reader.read_u8()?,
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},
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0x90 => Packet::SpiSetConfigRequest {
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destination: reader.read_u8()?,
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busno: reader.read_u8()?,
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flags: reader.read_u8()?,
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length: reader.read_u8()?,
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div: reader.read_u8()?,
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cs: reader.read_u8()?,
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},
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/* 0x91: was Packet::SpiSetXferRequest */
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0x92 => Packet::SpiWriteRequest {
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destination: reader.read_u8()?,
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busno: reader.read_u8()?,
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data: reader.read_u32()?,
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},
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0x93 => Packet::SpiReadRequest {
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destination: reader.read_u8()?,
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busno: reader.read_u8()?,
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},
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0x94 => Packet::SpiReadReply {
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succeeded: reader.read_bool()?,
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data: reader.read_u32()?,
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},
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0x95 => Packet::SpiBasicReply {
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succeeded: reader.read_bool()?,
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},
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0xb0 => {
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let destination = reader.read_u8()?;
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let id = reader.read_u32()?;
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let last = reader.read_bool()?;
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let length = reader.read_u16()?;
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let mut trace: [u8; DMA_TRACE_MAX_SIZE] = [0; DMA_TRACE_MAX_SIZE];
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reader.read_exact(&mut trace[0..length as usize])?;
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Packet::DmaAddTraceRequest {
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destination: destination,
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id: id,
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last: last,
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length: length as u16,
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trace: trace,
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}
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},
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0xb1 => Packet::DmaAddTraceReply {
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succeeded: reader.read_bool()?
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},
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0xb2 => Packet::DmaRemoveTraceRequest {
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destination: reader.read_u8()?,
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id: reader.read_u32()?
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},
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0xb3 => Packet::DmaRemoveTraceReply {
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succeeded: reader.read_bool()?
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},
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0xb4 => Packet::DmaPlaybackRequest {
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destination: reader.read_u8()?,
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id: reader.read_u32()?,
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timestamp: reader.read_u64()?
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},
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0xb5 => Packet::DmaPlaybackReply {
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succeeded: reader.read_bool()?
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},
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0xb6 => Packet::DmaPlaybackStatus {
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destination: reader.read_u8()?,
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id: reader.read_u32()?,
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error: reader.read_u8()?,
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channel: reader.read_u32()?,
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timestamp: reader.read_u64()?
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},
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ty => return Err(Error::UnknownPacket(ty)),
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})
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}
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pub fn write_to<W>(&self, writer: &mut W) -> Result<(), IoError>
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where W: Write + ?Sized {
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match *self {
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Packet::EchoRequest => writer.write_u8(0x00)?,
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Packet::EchoReply => writer.write_u8(0x01)?,
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Packet::ResetRequest => writer.write_u8(0x02)?,
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Packet::ResetAck => writer.write_u8(0x03)?,
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Packet::TSCAck => writer.write_u8(0x04)?,
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Packet::DestinationStatusRequest { destination } => {
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writer.write_u8(0x20)?;
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writer.write_u8(destination)?;
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}
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Packet::DestinationDownReply => writer.write_u8(0x21)?,
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Packet::DestinationOkReply => writer.write_u8(0x22)?,
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Packet::DestinationSequenceErrorReply { channel } => {
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writer.write_u8(0x23)?;
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writer.write_u16(channel)?;
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}
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Packet::DestinationCollisionReply { channel } => {
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writer.write_u8(0x24)?;
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writer.write_u16(channel)?;
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}
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Packet::DestinationBusyReply { channel } => {
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writer.write_u8(0x25)?;
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writer.write_u16(channel)?;
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}
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Packet::RoutingSetPath { destination, hops } => {
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writer.write_u8(0x30)?;
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writer.write_u8(destination)?;
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writer.write_all(&hops)?;
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}
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Packet::RoutingSetRank { rank } => {
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writer.write_u8(0x31)?;
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writer.write_u8(rank)?;
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}
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Packet::RoutingAck => writer.write_u8(0x32)?,
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Packet::MonitorRequest {
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destination,
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channel,
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probe,
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} => {
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writer.write_u8(0x40)?;
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writer.write_u8(destination)?;
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writer.write_u16(channel)?;
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writer.write_u8(probe)?;
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}
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Packet::MonitorReply { value } => {
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writer.write_u8(0x41)?;
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writer.write_u64(value)?;
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}
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Packet::InjectionRequest {
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destination,
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channel,
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overrd,
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value,
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} => {
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writer.write_u8(0x50)?;
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writer.write_u8(destination)?;
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writer.write_u16(channel)?;
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writer.write_u8(overrd)?;
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writer.write_u8(value)?;
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}
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Packet::InjectionStatusRequest {
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destination,
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channel,
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overrd,
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} => {
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writer.write_u8(0x51)?;
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writer.write_u8(destination)?;
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writer.write_u16(channel)?;
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writer.write_u8(overrd)?;
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}
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Packet::InjectionStatusReply { value } => {
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writer.write_u8(0x52)?;
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writer.write_u8(value)?;
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}
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Packet::I2cStartRequest { destination, busno } => {
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writer.write_u8(0x80)?;
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writer.write_u8(destination)?;
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writer.write_u8(busno)?;
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}
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Packet::I2cRestartRequest { destination, busno } => {
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writer.write_u8(0x81)?;
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writer.write_u8(destination)?;
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writer.write_u8(busno)?;
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}
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Packet::I2cStopRequest { destination, busno } => {
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writer.write_u8(0x82)?;
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writer.write_u8(destination)?;
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writer.write_u8(busno)?;
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}
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Packet::I2cWriteRequest {
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destination,
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busno,
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data,
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} => {
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writer.write_u8(0x83)?;
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writer.write_u8(destination)?;
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writer.write_u8(busno)?;
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writer.write_u8(data)?;
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}
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Packet::I2cWriteReply { succeeded, ack } => {
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writer.write_u8(0x84)?;
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writer.write_bool(succeeded)?;
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writer.write_bool(ack)?;
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}
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Packet::I2cReadRequest {
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destination,
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busno,
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ack,
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} => {
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writer.write_u8(0x85)?;
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writer.write_u8(destination)?;
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writer.write_u8(busno)?;
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writer.write_bool(ack)?;
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}
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Packet::I2cReadReply { succeeded, data } => {
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writer.write_u8(0x86)?;
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writer.write_bool(succeeded)?;
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writer.write_u8(data)?;
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}
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Packet::I2cBasicReply { succeeded } => {
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writer.write_u8(0x87)?;
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writer.write_bool(succeeded)?;
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}
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Packet::I2cSwitchSelectRequest {
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destination,
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busno,
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address,
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mask,
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} => {
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writer.write_u8(0x88)?;
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writer.write_u8(destination)?;
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writer.write_u8(busno)?;
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writer.write_u8(address)?;
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writer.write_u8(mask)?;
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}
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Packet::SpiSetConfigRequest {
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destination,
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busno,
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flags,
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length,
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div,
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cs,
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} => {
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writer.write_u8(0x90)?;
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writer.write_u8(destination)?;
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writer.write_u8(busno)?;
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writer.write_u8(flags)?;
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writer.write_u8(length)?;
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writer.write_u8(div)?;
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writer.write_u8(cs)?;
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}
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Packet::SpiWriteRequest {
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destination,
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busno,
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data,
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} => {
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writer.write_u8(0x92)?;
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writer.write_u8(destination)?;
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writer.write_u8(busno)?;
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writer.write_u32(data)?;
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}
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Packet::SpiReadRequest { destination, busno } => {
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writer.write_u8(0x93)?;
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writer.write_u8(destination)?;
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writer.write_u8(busno)?;
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}
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Packet::SpiReadReply { succeeded, data } => {
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writer.write_u8(0x94)?;
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writer.write_bool(succeeded)?;
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writer.write_u32(data)?;
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}
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Packet::SpiBasicReply { succeeded } => {
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writer.write_u8(0x95)?;
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writer.write_bool(succeeded)?;
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}
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Packet::DmaAddTraceRequest {
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destination,
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id,
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last,
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trace,
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length
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} => {
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writer.write_u8(0xb0)?;
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writer.write_u8(destination)?;
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writer.write_u32(id)?;
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writer.write_bool(last)?;
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// trace may be broken down to fit within drtio aux memory limit
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// will be reconstructed by satellite
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writer.write_u16(length)?;
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writer.write_all(&trace[0..length as usize])?;
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}
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Packet::DmaAddTraceReply { succeeded } => {
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writer.write_u8(0xb1)?;
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writer.write_bool(succeeded)?;
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}
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Packet::DmaRemoveTraceRequest { destination, id } => {
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writer.write_u8(0xb2)?;
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writer.write_u8(destination)?;
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writer.write_u32(id)?;
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}
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Packet::DmaRemoveTraceReply { succeeded } => {
|
|
writer.write_u8(0xb3)?;
|
|
writer.write_bool(succeeded)?;
|
|
}
|
|
Packet::DmaPlaybackRequest {
|
|
destination,
|
|
id,
|
|
timestamp
|
|
} => {
|
|
writer.write_u8(0xb4)?;
|
|
writer.write_u8(destination)?;
|
|
writer.write_u32(id)?;
|
|
writer.write_u64(timestamp)?;
|
|
}
|
|
Packet::DmaPlaybackReply { succeeded } => {
|
|
writer.write_u8(0xb5)?;
|
|
writer.write_bool(succeeded)?;
|
|
}
|
|
Packet::DmaPlaybackStatus {
|
|
destination,
|
|
id,
|
|
error,
|
|
channel,
|
|
timestamp
|
|
} => {
|
|
writer.write_u8(0xb6)?;
|
|
writer.write_u8(destination)?;
|
|
writer.write_u32(id)?;
|
|
writer.write_u8(error)?;
|
|
writer.write_u32(channel)?;
|
|
writer.write_u64(timestamp)?;
|
|
}
|
|
}
|
|
Ok(())
|
|
}
|
|
}
|