forked from M-Labs/artiq-zynq
67 lines
2.0 KiB
Python
67 lines
2.0 KiB
Python
from migen import *
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from migen.genlib.cdc import PulseSynchronizer, MultiReg
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from misoc.interconnect.csr import *
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class DDMTDSampler(Module):
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def __init__(self, cd_ref, main_clk_se):
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self.ref_beating = Signal()
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self.main_beating = Signal()
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# # #
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ref_beating_FF = Signal()
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main_beating_FF = Signal()
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self.specials += [
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# Two back to back FFs are used to prevent metastability
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Instance("FD", i_C=ClockSignal("helper"),
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i_D=cd_ref.clk, o_Q=ref_beating_FF),
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Instance("FD", i_C=ClockSignal("helper"),
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i_D=ref_beating_FF, o_Q=self.ref_beating),
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Instance("FD", i_C=ClockSignal("helper"),
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i_D=main_clk_se, o_Q=main_beating_FF),
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Instance("FD", i_C=ClockSignal("helper"),
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i_D=main_beating_FF, o_Q=self.main_beating)
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]
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class DDMTDDeglitcherFirstEdge(Module):
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def __init__(self, input_signal, blind_period=400):
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self.detect = Signal()
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rising = Signal()
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input_signal_r = Signal()
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# # #
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self.sync.helper += [
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input_signal_r.eq(input_signal),
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rising.eq(input_signal & ~input_signal_r)
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]
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blind_counter = Signal(max=blind_period)
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self.sync.helper += [
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If(blind_counter != 0, blind_counter.eq(blind_counter - 1)),
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If(input_signal_r, blind_counter.eq(blind_period - 1)),
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self.detect.eq(rising & (blind_counter == 0))
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]
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class DDMTD(Module):
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def __init__(self, counter, input_signal):
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# in helper clock domain
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self.h_tag = Signal(len(counter))
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self.h_tag_update = Signal()
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# # #
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deglitcher = DDMTDDeglitcherFirstEdge(input_signal)
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self.submodules += deglitcher
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self.sync.helper += [
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self.h_tag_update.eq(0),
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If(deglitcher.detect,
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self.h_tag_update.eq(1),
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self.h_tag.eq(counter)
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)
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] |