artiq-zynq/src/gateware
newell a410c40b50 ADD SPI to EBAZ4205 for AD9834 (#331)
Co-authored-by: newell <newell.jensen@gmail.com>
Co-committed-by: newell <newell.jensen@gmail.com>
2024-10-17 15:06:11 +08:00
..
acpki.py acpki: working 2020-09-09 21:24:49 +08:00
analyzer.py analyzer: report AXI bus errors 2020-07-20 19:51:22 +08:00
config.py refactor `write_rustc_cfg_file()` 2023-09-11 11:48:19 +08:00
ddmtd.py DDMTD: replace 1st edge to median edge deglitcher 2024-04-29 13:05:02 +08:00
dma.py dma: report AXI bus error 2020-07-21 12:47:20 +08:00
drtio_aux_controller.py drtio_aux_controller: support aux_buffer_count 2024-04-24 17:12:39 +08:00
ebaz4205.py ADD SPI to EBAZ4205 for AD9834 (#331) 2024-10-17 15:06:11 +08:00
endianness.py dma: fix endianness issues 2020-07-16 17:27:08 +08:00
kasli_soc.py allow toggling SED spread with flash config key 2024-07-09 18:11:20 +08:00
test_dma.py RTIO/SYS Clock merge 2023-02-17 15:52:43 +08:00
zc706.py allow toggling SED spread with flash config key 2024-07-09 18:11:20 +08:00
zynq_clocking.py zynq_clocking: Allow ext signal to set cur_clk csr 2023-11-07 18:55:08 +08:00