esavkin
/
artiq-zynq
forked from M-Labs/artiq-zynq
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Compare commits

base: esavkin:5c054cc90194b7647f78168b51bc452eed42f33e
Branches Tags
esavkin:master
esavkin:264-grabber-backport
esavkin:264-fix-grabber
esavkin:release-7
esavkin:add_80_to_125_clock_setting
esavkin:rustfmt-policy
esavkin:213-small-fix
esavkin:213-satman-sfp-fiber-support
esavkin:213-backport-sfp-fiber
esavkin:213-sfp-fiber-support
esavkin:102-update-rust
esavkin:1697-exception-format
esavkin:1697-rtiomap
esavkin:204-idle-kernel-typo
esavkin:reboot_support_mngmt
esavkin:release-6
M-Labs:release-8
M-Labs:master
M-Labs:release-7
M-Labs:release-6
...
compare: esavkin:8e0229d2651633fc6cd449b55a559742c56add18
Branches Tags
esavkin:master
esavkin:264-grabber-backport
esavkin:264-fix-grabber
esavkin:release-7
esavkin:add_80_to_125_clock_setting
esavkin:rustfmt-policy
esavkin:213-small-fix
esavkin:213-satman-sfp-fiber-support
esavkin:213-backport-sfp-fiber
esavkin:213-sfp-fiber-support
esavkin:102-update-rust
esavkin:1697-exception-format
esavkin:1697-rtiomap
esavkin:204-idle-kernel-typo
esavkin:reboot_support_mngmt
esavkin:release-6
M-Labs:release-8
M-Labs:master
M-Labs:release-7
M-Labs:release-6

2 Commits
5c054cc901 ... 8e0229d265

Author SHA1 Message Date
David Nadlinger 8e0229d265 si5324: crystal_{ref -> as_ckin2} [nfc] 
This makes it clear that by itself, the flag does not
cause the input mux to be changed.
 2022-12-17 01:33:50 +00:00
David Nadlinger 2ddb4d259f Undo most of Si5324 unification (5c054cc901) 
This reverts most of 5c054cc901, as it turns out that
si5324::setup is in fact also used to configure the
chip for operation as a DRTIO satellite.
 2022-12-17 01:31:14 +00:00
3 changed files with 102 additions and 84 deletions
Show Stats Expand all files Collapse all files

11
src/libboard_artiq/src/si5324.rs
View File

@ -29,7 +29,7 @@ pub struct FrequencySettings {
pub n31: u32, pub n31: u32,
pub n32: u32, pub n32: u32,
pub bwsel: u8, pub bwsel: u8,
pub crystal_ref: bool pub crystal_as_ckin2: bool
} }
pub enum Input { pub enum Input {
@ -84,7 +84,7 @@ fn map_frequency_settings(settings: &FrequencySettings) -> Result<FrequencySetti
n31: settings.n31 - 1, n31: settings.n31 - 1,
n32: settings.n32 - 1, n32: settings.n32 - 1,
bwsel: settings.bwsel, bwsel: settings.bwsel,
crystal_ref: settings.crystal_ref crystal_as_ckin2: settings.crystal_as_ckin2
}; };
Ok(r) Ok(r)
} }
@ -219,18 +219,15 @@ pub fn bypass(i2c: &mut I2c, input: Input, timer: &mut GlobalTimer) -> Result<()
Ok(()) Ok(())
} }
pub fn setup(i2c: &mut I2c, settings: &FrequencySettings, ext_input: Input, timer: &mut GlobalTimer) -> Result<()> { pub fn setup(i2c: &mut I2c, settings: &FrequencySettings, input: Input, timer: &mut GlobalTimer) -> Result<()> {
let s = map_frequency_settings(settings)?; let s = map_frequency_settings(settings)?;
// FREE_RUN=1 routes XA/XB to CKIN2.
let input = if settings.crystal_ref { Input::Ckin2 } else { ext_input };
let cksel_reg = match input { let cksel_reg = match input {
Input::Ckin1 => 0b00, Input::Ckin1 => 0b00,
Input::Ckin2 => 0b01, Input::Ckin2 => 0b01,
}; };
init(i2c, timer)?; init(i2c, timer)?;
if settings.crystal_ref { if settings.crystal_as_ckin2 {
rmw(i2c, 0, |v| v | 0x40)?; // FREE_RUN=1 rmw(i2c, 0, |v| v | 0x40)?; // FREE_RUN=1
} }
rmw(i2c, 2, |v| (v & 0x0f) | (s.bwsel << 4))?; rmw(i2c, 2, |v| (v & 0x0f) | (s.bwsel << 4))?;

171
src/runtime/src/rtio_clocking.rs
View File

@ -121,100 +121,121 @@ const SI5324_EXT_INPUT: si5324::Input = si5324::Input::Ckin1;
#[cfg(has_si5324)] #[cfg(has_si5324)]
fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) { fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) {
let si5324_settings = match clk { let (si5324_settings, si5324_ref_input) = match clk {
RtioClock::Ext0_Synth0_10to125 => { // 125 MHz output from 10 MHz CLKINx reference, 504 Hz BW RtioClock::Ext0_Synth0_10to125 => { // 125 MHz output from 10 MHz CLKINx reference, 504 Hz BW
info!("using 10MHz reference to make 125MHz RTIO clock with PLL"); info!("using 10MHz reference to make 125MHz RTIO clock with PLL");
si5324::FrequencySettings { (
n1_hs : 10, si5324::FrequencySettings {
nc1_ls : 4, n1_hs : 10,
n2_hs : 10, nc1_ls : 4,
n2_ls : 300, n2_hs : 10,
n31 : 6, n2_ls : 300,
n32 : 6, n31 : 6,
bwsel : 4, n32 : 6,
crystal_ref: false bwsel : 4,
} crystal_as_ckin2: false
},
SI5324_EXT_INPUT
)
}, },
RtioClock::Ext0_Synth0_100to125 => { // 125MHz output, from 100MHz CLKINx reference, 586 Hz loop bandwidth RtioClock::Ext0_Synth0_100to125 => { // 125MHz output, from 100MHz CLKINx reference, 586 Hz loop bandwidth
info!("using 100MHz reference to make 125MHz RTIO clock with PLL"); info!("using 100MHz reference to make 125MHz RTIO clock with PLL");
si5324::FrequencySettings { (
n1_hs : 10, si5324::FrequencySettings {
nc1_ls : 4, n1_hs : 10,
n2_hs : 10, nc1_ls : 4,
n2_ls : 260, n2_hs : 10,
n31 : 52, n2_ls : 260,
n32 : 52, n31 : 52,
bwsel : 4, n32 : 52,
crystal_ref: false bwsel : 4,
} crystal_as_ckin2: false
},
SI5324_EXT_INPUT
)
}, },
RtioClock::Ext0_Synth0_125to125 => { // 125MHz output, from 125MHz CLKINx reference, 606 Hz loop bandwidth RtioClock::Ext0_Synth0_125to125 => { // 125MHz output, from 125MHz CLKINx reference, 606 Hz loop bandwidth
info!("using 125MHz reference to make 125MHz RTIO clock with PLL"); info!("using 125MHz reference to make 125MHz RTIO clock with PLL");
si5324::FrequencySettings { (
n1_hs : 5, si5324::FrequencySettings {
nc1_ls : 8, n1_hs : 5,
n2_hs : 7, nc1_ls : 8,
n2_ls : 360, n2_hs : 7,
n31 : 63, n2_ls : 360,
n32 : 63, n31 : 63,
bwsel : 4, n32 : 63,
crystal_ref: false bwsel : 4,
} crystal_as_ckin2: false
},
SI5324_EXT_INPUT
)
}, },
RtioClock::Int_150 => { // 150MHz output, from crystal RtioClock::Int_150 => { // 150MHz output, from crystal
info!("using internal 150MHz RTIO clock"); info!("using internal 150MHz RTIO clock");
si5324::FrequencySettings { (
n1_hs : 9, si5324::FrequencySettings {
nc1_ls : 4, n1_hs : 9,
n2_hs : 10, nc1_ls : 4,
n2_ls : 33732, n2_hs : 10,
n31 : 7139, n2_ls : 33732,
n32 : 7139, n31 : 7139,
bwsel : 3, n32 : 7139,
crystal_ref: true bwsel : 3,
} crystal_as_ckin2: true
},
si5324::Input::Ckin2
)
}, },
RtioClock::Int_100 => { // 100MHz output, from crystal RtioClock::Int_100 => { // 100MHz output, from crystal
info!("using internal 100MHz RTIO clock"); info!("using internal 100MHz RTIO clock");
si5324::FrequencySettings { (
n1_hs : 9, si5324::FrequencySettings {
nc1_ls : 6, n1_hs : 9,
n2_hs : 10, nc1_ls : 6,
n2_ls : 33732, n2_hs : 10,
n31 : 7139, n2_ls : 33732,
n32 : 7139, n31 : 7139,
bwsel : 3, n32 : 7139,
crystal_ref: true bwsel : 3,
} crystal_as_ckin2: true
},
si5324::Input::Ckin2
)
}, },
RtioClock::Int_125 => { // 125MHz output, from crystal, 7 Hz RtioClock::Int_125 => { // 125MHz output, from crystal, 7 Hz
info!("using internal 125MHz RTIO clock"); info!("using internal 125MHz RTIO clock");
si5324::FrequencySettings { (
n1_hs : 10, si5324::FrequencySettings {
nc1_ls : 4, n1_hs : 10,
n2_hs : 10, nc1_ls : 4,
n2_ls : 19972, n2_hs : 10,
n31 : 4565, n2_ls : 19972,
n32 : 4565, n31 : 4565,
bwsel : 4, n32 : 4565,
crystal_ref: true bwsel : 4,
} crystal_as_ckin2: true
} },
_ => { // 125MHz output like above, default (if chosen option is not supported) si5324::Input::Ckin2
warn!("rtio_clock setting '{:?}' is not supported. Falling back to default internal 125MHz RTIO clock.", clk); )
si5324::FrequencySettings { },
n1_hs : 10, _ => { // same setting as Int_125, but fallback to default
nc1_ls : 4, warn!("rtio_clock setting '{:?}' is unsupported. Falling back to default internal 125MHz RTIO clock.", clk);
n2_hs : 10, (
n2_ls : 19972, si5324::FrequencySettings {
n31 : 4565, n1_hs : 10,
n32 : 4565, nc1_ls : 4,
bwsel : 4, n2_hs : 10,
crystal_ref: true n2_ls : 19972,
} n31 : 4565,
n32 : 4565,
bwsel : 4,
crystal_as_ckin2: true
},
si5324::Input::Ckin2
)
} }
}; };
si5324::setup(i2c, &si5324_settings, SI5324_EXT_INPUT, timer).expect("cannot initialize Si5324"); si5324::setup(i2c, &si5324_settings, si5324_ref_input, timer).expect("cannot initialize Si5324");
} }
pub fn init(timer: &mut GlobalTimer, cfg: &Config) { pub fn init(timer: &mut GlobalTimer, cfg: &Config) {

4
src/satman/src/main.rs
View File

@ -428,7 +428,7 @@ const SI5324_SETTINGS: si5324::FrequencySettings
n31 : 63, n31 : 63,
n32 : 63, n32 : 63,
bwsel : 4, bwsel : 4,
crystal_ref: true crystal_as_ckin2: true
}; };
#[cfg(all(has_si5324, rtio_frequency = "100.0"))] #[cfg(all(has_si5324, rtio_frequency = "100.0"))]
@ -441,7 +441,7 @@ const SI5324_SETTINGS: si5324::FrequencySettings
n31 : 50, n31 : 50,
n32 : 50, n32 : 50,
bwsel : 4, bwsel : 4,
crystal_ref: true crystal_as_ckin2: true
}; };
static mut LOG_BUFFER: [u8; 1<<17] = [0; 1<<17]; static mut LOG_BUFFER: [u8; 1<<17] = [0; 1<<17];