forked from M-Labs/artiq-zynq
kasli_soc: add fix_serdes_timing_path
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@ -15,6 +15,7 @@ from misoc.integration import cpu_interface
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from artiq.coredevice import jsondesc
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from artiq.gateware import rtio, eem_7series
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from artiq.gateware.rtio.phy import ttl_simple
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from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
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from artiq.gateware.rtio.xilinx_clocking import RTIOClockMultiplier
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from artiq.gateware.drtio.transceiver import gtx_7series
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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@ -138,6 +139,7 @@ class GenericStandalone(SoCCore):
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self.platform.add_false_path_constraints(
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self.ps7.cd_sys.clk,
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self.rtio_crg.cd_rtio.clk)
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fix_serdes_timing_path(platform)
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self.rtio_channels = []
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
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@ -225,6 +227,7 @@ class GenericMaster(SoCCore):
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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self.submodules.rtio_crg = RTIOClockMultiplier(rtio_clk_freq)
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self.csr_devices.append("rtio_crg")
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fix_serdes_timing_path(platform)
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self.rustc_cfg["has_si5324"] = None
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self.rustc_cfg["si5324_soft_reset"] = None
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@ -341,6 +344,7 @@ class GenericSatellite(SoCCore):
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self.submodules.rtio_crg = RTIOClockMultiplier(rtio_clk_freq)
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self.csr_devices.append("rtio_crg")
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self.rustc_cfg["has_rtio_crg"] = None
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fix_serdes_timing_path(platform)
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data_pads = [platform.request("sfp", i) for i in range(4)]
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