forked from M-Labs/artiq-zynq
increase CSR bus width to 32 bits
Before: Minimum interval for sustained TTL output switching ... 1.554e-06 After: Minimum interval for sustained TTL output switching ... 5.17e-07
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@ -18,7 +18,7 @@ class ZC706(SoCCore):
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platform.toolchain.bitstream_commands.extend([
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platform.toolchain.bitstream_commands.extend([
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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])
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])
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SoCCore.__init__(self, platform=platform, ident=self.__class__.__name__)
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=self.__class__.__name__)
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platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
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platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
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platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
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platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
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