forked from M-Labs/artiq-zynq
Revert i2c wrapper refactor, untie io_expander from it
Signed-off-by: Egor Savkin <es@m-labs.hk>
This commit is contained in:
parent
e51a5728e0
commit
8822f2493e
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@ -1,83 +0,0 @@
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use libboard_zynq;
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pub static mut I2C_BUS: Option<libboard_zynq::i2c::I2c> = None;
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pub fn start() -> Result<(), &'static str> {
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unsafe {
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if (&mut I2C_BUS).as_mut().unwrap().start().is_err() {
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Err("I2C start failed")
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} else {
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Ok(())
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}
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}
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}
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pub fn restart() -> Result<(), &'static str> {
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unsafe {
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if (&mut I2C_BUS).as_mut().unwrap().restart().is_err() {
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Err("I2C restart failed")
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} else {
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Ok(())
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}
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}
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}
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pub fn stop() -> Result<(), &'static str> {
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unsafe {
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if (&mut I2C_BUS).as_mut().unwrap().stop().is_err() {
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Err("I2C stop failed")
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} else {
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Ok(())
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}
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}
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}
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pub fn write(data: i32) -> Result<bool, &'static str> {
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unsafe {
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match (&mut I2C_BUS).as_mut().unwrap().write(data as u8) {
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Ok(r) =>Ok(r),
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Err(_) => Err("I2C write failed"),
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}
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}
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}
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pub fn read(ack: bool) -> Result<i32, &'static str> {
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unsafe {
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match (&mut I2C_BUS).as_mut().unwrap().read(ack) {
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Ok(r) => Ok(r as i32),
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Err(_) => Err("I2C read failed"),
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}
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}
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}
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pub fn pca954x_select(address: i32, channel: Option<u8>) -> Result<(), &'static str> {
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unsafe {
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if (&mut I2C_BUS).as_mut().unwrap().pca954x_select(address as u8, channel).is_err() {
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Err("switch select failed")
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} else {
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Ok(())
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}
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}
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}
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pub fn switch_select(address: i32, mask: i32) -> Result<(), &'static str> {
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let ch = match mask { //decode from mainline, PCA9548-centric API
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0x00 => None,
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0x01 => Some(0),
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0x02 => Some(1),
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0x04 => Some(2),
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0x08 => Some(3),
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0x10 => Some(4),
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0x20 => Some(5),
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0x40 => Some(6),
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0x80 => Some(7),
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_ => return Err("switch select supports only one channel")
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};
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pca954x_select(address, ch)
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}
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pub fn init() {
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let mut i2c = libboard_zynq::i2c::I2c::i2c0();
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i2c.init().expect("I2C bus initialization failed");
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unsafe { I2C_BUS = Some(i2c) };
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}
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@ -1,4 +1,4 @@
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use crate::i2c;
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use libboard_zynq::i2c;
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use log::info;
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// Only the bare minimum registers. Bits/IO connections equivalent between IC types.
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@ -10,9 +10,9 @@ struct Registers {
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gpiob: u8, // Output Port 1
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}
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pub struct IoExpander {
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port: u8,
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address: i32,
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pub struct IoExpander<'a> {
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i2c: &'a mut i2c::I2c,
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address: u8,
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iodir: [u8; 2],
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out_current: [u8; 2],
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out_target: [u8; 2],
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@ -20,13 +20,13 @@ pub struct IoExpander {
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}
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impl IoExpander {
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pub fn new(index: u8) -> Result<Self, &'static str> {
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impl<'a> IoExpander<'a> {
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pub fn new(i2c: &'a mut i2c::I2c, index: u8) -> Result<Self, &'static str> {
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// Both expanders on SHARED I2C bus
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let mut io_expander = match index {
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0 => IoExpander {
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port: 11,
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i2c,
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address: 0x40,
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iodir: [0xff; 2],
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out_current: [0; 2],
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@ -39,7 +39,7 @@ impl IoExpander {
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},
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},
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1 => IoExpander {
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port: 11,
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i2c,
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address: 0x42,
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iodir: [0xff; 2],
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out_current: [0; 2],
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@ -72,32 +72,31 @@ impl IoExpander {
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Ok(io_expander)
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}
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fn select(&self) -> Result<(), &'static str> {
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let mask: u16 = 1 << self.port;
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i2c::switch_select(0x70, mask as u8 as i32)?;
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i2c::switch_select(0x71, (mask >> 8) as u8 as i32)?;
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fn select(&mut self) -> Result<(), &'static str> {
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self.i2c.pca954x_select(0x70, None)?;
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self.i2c.pca954x_select(0x71, Some(3))?;
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Ok(())
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}
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fn write(&self, addr: u8, value: u8) -> Result<(), &'static str> {
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i2c::start()?;
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i2c::write(self.address as i32)?;
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i2c::write(addr as i32)?;
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i2c::write(value as i32)?;
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i2c::stop()?;
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fn write(&mut self, addr: u8, value: u8) -> Result<(), &'static str> {
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self.i2c.start()?;
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self.i2c.write(self.address)?;
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self.i2c.write(addr)?;
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self.i2c.write(value)?;
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self.i2c.stop()?;
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Ok(())
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}
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fn check_ack(&self) -> Result<bool, &'static str> {
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fn check_ack(&mut self) -> Result<bool, &'static str> {
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// Check for ack from io expander
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self.select()?;
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i2c::start()?;
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let ack = i2c::write(self.address)?;
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i2c::stop()?;
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self.i2c.start()?;
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let ack = self.i2c.write(self.address)?;
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self.i2c.stop()?;
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Ok(ack)
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}
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fn update_iodir(&self) -> Result<(), &'static str> {
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fn update_iodir(&mut self) -> Result<(), &'static str> {
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self.write(self.registers.iodira, self.iodir[0])?;
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self.write(self.registers.iodirb, self.iodir[1])?;
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Ok(())
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@ -27,7 +27,6 @@ pub mod drtioaux_async;
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#[cfg(has_drtio)]
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#[path = "../../../build/mem.rs"]
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pub mod mem;
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pub mod i2c;
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#[cfg(feature = "target_kasli_soc")]
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pub mod io_expander;
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@ -0,0 +1,90 @@
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use libboard_zynq;
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use crate::artiq_raise;
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pub static mut I2C_BUS: Option<libboard_zynq::i2c::I2c> = None;
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pub extern fn start(busno: i32) {
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if busno > 0 {
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artiq_raise!("I2CError", "I2C bus could not be accessed");
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}
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unsafe {
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if (&mut I2C_BUS).as_mut().unwrap().start().is_err() {
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artiq_raise!("I2CError", "I2C start failed");
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}
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}
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}
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pub extern fn restart(busno: i32) {
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if busno > 0 {
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artiq_raise!("I2CError", "I2C bus could not be accessed");
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}
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unsafe {
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if (&mut I2C_BUS).as_mut().unwrap().restart().is_err() {
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artiq_raise!("I2CError", "I2C restart failed");
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}
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}
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}
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pub extern fn stop(busno: i32) {
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if busno > 0 {
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artiq_raise!("I2CError", "I2C bus could not be accessed");
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}
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unsafe {
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if (&mut I2C_BUS).as_mut().unwrap().stop().is_err() {
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artiq_raise!("I2CError", "I2C stop failed");
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}
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}
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}
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pub extern fn write(busno: i32, data: i32) -> bool {
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if busno > 0 {
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artiq_raise!("I2CError", "I2C bus could not be accessed");
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}
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unsafe {
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match (&mut I2C_BUS).as_mut().unwrap().write(data as u8) {
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Ok(r) => r,
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Err(_) => artiq_raise!("I2CError", "I2C write failed"),
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}
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}
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}
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pub extern fn read(busno: i32, ack: bool) -> i32 {
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if busno > 0 {
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artiq_raise!("I2CError", "I2C bus could not be accessed");
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}
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unsafe {
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match (&mut I2C_BUS).as_mut().unwrap().read(ack) {
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Ok(r) => r as i32,
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Err(_) => artiq_raise!("I2CError", "I2C read failed"),
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}
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}
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}
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pub extern fn switch_select(busno: i32, address: i32, mask: i32) {
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if busno > 0 {
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artiq_raise!("I2CError", "I2C bus could not be accessed");
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}
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let ch = match mask { //decode from mainline, PCA9548-centric API
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0x00 => None,
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0x01 => Some(0),
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0x02 => Some(1),
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0x04 => Some(2),
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0x08 => Some(3),
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0x10 => Some(4),
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0x20 => Some(5),
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0x40 => Some(6),
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0x80 => Some(7),
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_ => artiq_raise!("I2CError", "switch select supports only one channel")
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};
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unsafe {
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if (&mut I2C_BUS).as_mut().unwrap().pca954x_select(address as u8, ch).is_err() {
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artiq_raise!("I2CError", "switch select failed");
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}
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}
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}
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pub fn init() {
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let mut i2c = libboard_zynq::i2c::I2c::i2c0();
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i2c.init().expect("I2C bus initialization failed");
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unsafe { I2C_BUS = Some(i2c) };
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}
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@ -21,7 +21,7 @@ use nb;
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use void::Void;
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use libconfig::Config;
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use libcortex_a9::l2c::enable_l2_cache;
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use libboard_artiq::{logger, identifier_read, pl, i2c, io_expander};
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use libboard_artiq::{logger, identifier_read, pl, io_expander};
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const ASYNC_ERROR_COLLISION: u8 = 1 << 0;
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const ASYNC_ERROR_BUSY: u8 = 1 << 1;
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@ -45,6 +45,7 @@ mod panic;
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mod mgmt;
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mod analyzer;
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mod irq;
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mod i2c;
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static mut SEEN_ASYNC_ERRORS: u8 = 0;
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@ -114,21 +115,17 @@ pub fn main_core0() {
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#[cfg(feature = "target_kasli_soc")]
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{
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let (mut io_expander0, mut io_expander1) = (io_expander::IoExpander::new(0).unwrap(), io_expander::IoExpander::new(1).unwrap());
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io_expander0.init().expect("I2C I/O expander #0 initialization failed");
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io_expander1.init().expect("I2C I/O expander #1 initialization failed");
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let i2c = unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() };
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for expander_i in 0..2 {
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let mut io_expander = io_expander::IoExpander::new(i2c, expander_i).unwrap();
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io_expander.init().expect("I2C I/O expander #0 initialization failed");
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// Actively drive TX_DISABLE to false on SFP0..3
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io_expander0.set_oe(0, 1 << 1).unwrap();
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io_expander0.set_oe(1, 1 << 1).unwrap();
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io_expander1.set_oe(0, 1 << 1).unwrap();
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io_expander1.set_oe(1, 1 << 1).unwrap();
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io_expander0.set(0, 1, false);
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io_expander0.set(1, 1, false);
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io_expander1.set(0, 1, false);
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io_expander1.set(1, 1, false);
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io_expander0.service().unwrap();
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io_expander1.service().unwrap();
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io_expander.set_oe(0, 1 << 1).unwrap();
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io_expander.set_oe(1, 1 << 1).unwrap();
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io_expander.set(0, 1, false);
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io_expander.set(1, 1, false);
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io_expander.service().unwrap();
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}
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}
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let cfg = match Config::new() {
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@ -18,12 +18,11 @@ extern crate unwind;
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extern crate alloc;
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use libboard_zynq::{timer::GlobalTimer, time::Milliseconds, print, println, mpcore, gic, stdio};
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use libboard_zynq::{i2c::I2c, timer::GlobalTimer, time::Milliseconds, print, println, mpcore, gic, stdio};
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use libsupport_zynq::ram;
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#[cfg(has_si5324)]
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use libboard_artiq::si5324;
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use libboard_artiq::{pl::csr, drtio_routing, drtioaux, logger,
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identifier_read, i2c, io_expander};
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use libboard_artiq::{pl::csr, drtio_routing, drtioaux, logger, identifier_read, io_expander};
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use libcortex_a9::{spin_lock_yield, interrupt_handler, regs::{MPIDR, SP}, notify_spin_lock, asm, l2c::enable_l2_cache};
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use libregister::{RegisterW, RegisterR};
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#[cfg(feature = "target_kasli_soc")]
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@ -85,7 +84,7 @@ macro_rules! forward {
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fn process_aux_packet(_repeaters: &mut [repeater::Repeater],
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_routing_table: &mut drtio_routing::RoutingTable, _rank: &mut u8,
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packet: drtioaux::Packet, timer: &mut GlobalTimer) -> Result<(), drtioaux::Error> {
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packet: drtioaux::Packet, timer: &mut GlobalTimer, i2c: &mut I2c) -> Result<(), drtioaux::Error> {
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// In the code below, *_chan_sel_write takes an u8 if there are fewer than 256 channels,
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// and u16 otherwise; hence the `as _` conversion.
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match packet {
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@ -254,22 +253,22 @@ fn process_aux_packet(_repeaters: &mut [repeater::Repeater],
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drtioaux::Packet::I2cStartRequest { destination: _destination, busno: _busno } => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
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let succeeded = i2c::start().is_ok();
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let succeeded = i2c.start().is_ok();
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drtioaux::send(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded })
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}
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drtioaux::Packet::I2cRestartRequest { destination: _destination, busno: _busno } => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
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let succeeded = i2c::restart().is_ok();
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let succeeded = i2c.restart().is_ok();
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drtioaux::send(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded })
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}
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drtioaux::Packet::I2cStopRequest { destination: _destination, busno: _busno } => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
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let succeeded = i2c::stop().is_ok();
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let succeeded = i2c.stop().is_ok();
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drtioaux::send(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded })
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}
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drtioaux::Packet::I2cWriteRequest { destination: _destination, busno: _busno, data } => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
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match i2c::write(data as i32) {
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match i2c.write(data) {
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Ok(ack) => drtioaux::send(0,
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&drtioaux::Packet::I2cWriteReply { succeeded: true, ack: ack }),
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Err(_) => drtioaux::send(0,
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@ -278,9 +277,9 @@ fn process_aux_packet(_repeaters: &mut [repeater::Repeater],
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}
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drtioaux::Packet::I2cReadRequest { destination: _destination, busno: _busno, ack } => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
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match i2c::read(ack) {
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match i2c.read(ack) {
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Ok(data) => drtioaux::send(0,
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&drtioaux::Packet::I2cReadReply { succeeded: true, data: data as u8 }),
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&drtioaux::Packet::I2cReadReply { succeeded: true, data: data }),
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Err(_) => drtioaux::send(0,
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&drtioaux::Packet::I2cReadReply { succeeded: false, data: 0xff })
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}
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@ -299,7 +298,7 @@ fn process_aux_packet(_repeaters: &mut [repeater::Repeater],
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0x80 => Some(7),
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_ => { return drtioaux::send(0, &drtioaux::Packet::I2cBasicReply { succeeded: false }); }
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};
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let succeeded = i2c::pca954x_select(address as i32, ch).is_ok();
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let succeeded = i2c.pca954x_select(address, ch).is_ok();
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drtioaux::send(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded })
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}
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@ -340,11 +339,11 @@ fn process_aux_packet(_repeaters: &mut [repeater::Repeater],
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fn process_aux_packets(repeaters: &mut [repeater::Repeater],
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routing_table: &mut drtio_routing::RoutingTable, rank: &mut u8,
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timer: &mut GlobalTimer) {
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||||
timer: &mut GlobalTimer, i2c: &mut I2c) {
|
||||
let result =
|
||||
drtioaux::recv(0).and_then(|packet| {
|
||||
if let Some(packet) = packet {
|
||||
process_aux_packet(repeaters, routing_table, rank, packet, timer)
|
||||
process_aux_packet(repeaters, routing_table, rank, packet, timer, i2c)
|
||||
} else {
|
||||
Ok(())
|
||||
}
|
||||
|
|
@ -448,32 +447,24 @@ pub extern fn main_core0() -> i32 {
|
|||
|
||||
ram::init_alloc_core0();
|
||||
|
||||
i2c::init();
|
||||
|
||||
let mut i2c = I2c::i2c0();
|
||||
i2c.init().expect("I2C initialization failed");
|
||||
#[cfg(feature = "target_kasli_soc")]
|
||||
{
|
||||
let (mut io_expander0, mut io_expander1) = (io_expander::IoExpander::new(0).unwrap(), io_expander::IoExpander::new(1).unwrap());
|
||||
io_expander0.init().expect("I2C I/O expander #0 initialization failed");
|
||||
io_expander1.init().expect("I2C I/O expander #1 initialization failed");
|
||||
|
||||
for expander_i in 0..2 {
|
||||
let mut io_expander = io_expander::IoExpander::new(&mut i2c, expander_i).unwrap();
|
||||
io_expander.init().expect("I2C I/O expander #0 initialization failed");
|
||||
// Actively drive TX_DISABLE to false on SFP0..3
|
||||
io_expander0.set_oe(0, 1 << 1).unwrap();
|
||||
io_expander0.set_oe(1, 1 << 1).unwrap();
|
||||
io_expander1.set_oe(0, 1 << 1).unwrap();
|
||||
io_expander1.set_oe(1, 1 << 1).unwrap();
|
||||
io_expander0.set(0, 1, false);
|
||||
io_expander0.set(1, 1, false);
|
||||
io_expander1.set(0, 1, false);
|
||||
io_expander1.set(1, 1, false);
|
||||
io_expander0.service().unwrap();
|
||||
io_expander1.service().unwrap();
|
||||
io_expander.set_oe(0, 1 << 1).unwrap();
|
||||
io_expander.set_oe(1, 1 << 1).unwrap();
|
||||
io_expander.set(0, 1, false);
|
||||
io_expander.set(1, 1, false);
|
||||
io_expander.service().unwrap();
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(has_si5324)]
|
||||
{
|
||||
let mut i2c = unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() };
|
||||
si5324::setup(&mut i2c, &SI5324_SETTINGS, si5324::Input::Ckin1, &mut timer).expect("cannot initialize Si5324");
|
||||
}
|
||||
|
||||
timer.delay_us(100_000);
|
||||
info!("Switching SYS clocks...");
|
||||
|
|
@ -517,7 +508,6 @@ pub extern fn main_core0() -> i32 {
|
|||
info!("uplink is up, switching to recovered clock");
|
||||
#[cfg(has_siphaser)]
|
||||
{
|
||||
let mut i2c = unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() };
|
||||
si5324::siphaser::select_recovered_clock(&mut i2c, true, &mut timer).expect("failed to switch clocks");
|
||||
si5324::siphaser::calibrate_skew(&mut timer).expect("failed to calibrate skew");
|
||||
}
|
||||
|
|
@ -528,7 +518,7 @@ pub extern fn main_core0() -> i32 {
|
|||
|
||||
while drtiosat_link_rx_up() {
|
||||
drtiosat_process_errors();
|
||||
process_aux_packets(&mut repeaters, &mut routing_table, &mut rank, &mut timer);
|
||||
process_aux_packets(&mut repeaters, &mut routing_table, &mut rank, &mut timer, &mut i2c);
|
||||
#[allow(unused_mut)]
|
||||
for mut rep in repeaters.iter_mut() {
|
||||
rep.service(&routing_table, rank, &mut timer);
|
||||
|
|
@ -552,12 +542,9 @@ pub extern fn main_core0() -> i32 {
|
|||
drtiosat_tsc_loaded();
|
||||
info!("uplink is down, switching to local oscillator clock");
|
||||
#[cfg(has_siphaser)]
|
||||
{
|
||||
let mut i2c = unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() };
|
||||
si5324::siphaser::select_recovered_clock(&mut i2c, false, &mut timer).expect("failed to switch clocks");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
extern "C" {
|
||||
static mut __stack1_start: u32;
|
||||
|
|
|
|||
Loading…
Reference in New Issue