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@ -46,6 +46,9 @@ class ZC706(SoCCore):
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self.comb += self.rtio.cri.connect(self.rtio_core.cri)
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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def write_csr_file(soc, filename):
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with open(filename, "w") as f:
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