forked from M-Labs/artiq-zynq
86 lines
3.9 KiB
Python
86 lines
3.9 KiB
Python
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"""Auxiliary controller, common to satellite and master"""
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from artiq.gateware.drtio.aux_controller import Transmitter, Receiver
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from migen.fhdl.simplify import FullMemoryWE
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from misoc.interconnect.csr import *
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from migen_axi.interconnect.sram import SRAM
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from migen_axi.interconnect import axi
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max_packet = 1024
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class _DRTIOAuxControllerBase(Module):
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def __init__(self, link_layer):
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self.bus = axi.Interface()
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self.submodules.transmitter = Transmitter(link_layer, len(self.bus.w.data))
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self.submodules.receiver = Receiver(link_layer, len(self.bus.w.data))
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def get_csrs(self):
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return self.transmitter.get_csrs() + self.receiver.get_csrs()
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# TODO: FullMemoryWE should be applied by migen.build
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@FullMemoryWE()
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class DRTIOAuxControllerAxi(_DRTIOAuxControllerBase):
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def __init__(self, link_layer):
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_DRTIOAuxControllerBase.__init__(self, link_layer)
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tx_sdram_if = SRAM(self.transmitter.mem, read_only=False)
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rx_sdram_if = SRAM(self.receiver.mem, read_only=True)
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aw_decoder = axi.AddressDecoder(self.bus.aw,
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[(lambda a: a[log2_int(max_packet)] == 0, tx_sdram_if.bus.aw),
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(lambda a: a[log2_int(max_packet)] == 1, rx_sdram_if.bus.aw)],
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register=True)
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ar_decoder = axi.AddressDecoder(self.bus.ar,
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[(lambda a: a[log2_int(max_packet)] == 0, tx_sdram_if.bus.ar),
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(lambda a: a[log2_int(max_packet)] == 1, rx_sdram_if.bus.ar)],
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register=True)
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# unlike wb, axi address decoder only connects ar/aw lanes,
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# the rest must also be connected!
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# not quite unlike an address decoder itself.
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# connect bus.b with tx.b
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self.comb += [tx_sdram_if.bus.b.ready.eq(self.bus.b.ready),
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self.bus.b.id.eq(tx_sdram_if.bus.b.id),
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self.bus.b.resp.eq(tx_sdram_if.bus.b.resp),
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self.bus.b.valid.eq(tx_sdram_if.bus.b.valid)]
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# connect bus.w with tx.w
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# no worries about w.valid and slave sel here, only tx will be written to
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self.comb += [tx_sdram_if.bus.w.id.eq(self.bus.w.id),
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tx_sdram_if.bus.w.data.eq(self.bus.w.data),
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tx_sdram_if.bus.w.strb.eq(self.bus.w.strb),
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tx_sdram_if.bus.w.last.eq(self.bus.w.last),
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tx_sdram_if.bus.w.valid.eq(self.bus.w.valid),
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self.bus.w.ready.eq(tx_sdram_if.bus.w.ready)]
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# connect bus.r with rx.r and tx.r w/o data
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self.comb += [self.bus.r.id.eq(rx_sdram_if.bus.r.id | tx_sdram_if.bus.r.id),
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#self.bus.r.data.eq(rx_sdram_if.bus.r.data | tx_sdram_if.bus.r.data),
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self.bus.r.resp.eq(rx_sdram_if.bus.r.resp | tx_sdram_if.bus.r.resp),
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self.bus.r.last.eq(rx_sdram_if.bus.r.last | tx_sdram_if.bus.r.last),
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self.bus.r.valid.eq(rx_sdram_if.bus.r.valid | tx_sdram_if.bus.r.valid),
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rx_sdram_if.bus.r.ready.eq(self.bus.r.ready),
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tx_sdram_if.bus.r.ready.eq(self.bus.r.ready)]
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# connect read data after being masked
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masked = [Replicate(rx_sdram_if.bus.r.valid,
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len(self.bus.r.data)
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) & rx_sdram_if.bus.r.data,
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Replicate(tx_sdram_if.bus.r.valid,
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len(self.bus.r.data)
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) & tx_sdram_if.bus.r.data]
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self.comb += self.bus.r.data.eq(reduce(or_, masked))
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self.submodules += tx_sdram_if, rx_sdram_if, aw_decoder, ar_decoder
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@FullMemoryWE()
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class DRTIOAuxControllerBare(_DRTIOAuxControllerBase):
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# Barebones version of the AuxController. No SRAM, no decoders.
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# add memories manually from tx and rx in target code.
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def get_tx_port(self):
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return self.transmitter.mem.get_port(write_capable=True)
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def get_rx_port(self):
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return self.receiver.mem.get_port(write_capable=False)
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def get_mem_size(self):
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return max_packet
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