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dsleung
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Joined on
2020-05-28
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M-Labs/riscv-formal-nmigen
2020-07-22 12:50:57 +08:00
b3fdeea0f8
Add LHU instruction for RV32I
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M-Labs/riscv-formal-nmigen
2020-07-22 12:47:05 +08:00
37f21b317b
Add LBU instruction for RV32I
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M-Labs/riscv-formal-nmigen
2020-07-22 12:42:55 +08:00
83c9b8c664
Add LW instruction for RV32I
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M-Labs/riscv-formal-nmigen
2020-07-22 12:31:00 +08:00
fb002c622e
Add LH instruction for RV32I
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M-Labs/riscv-formal-nmigen
2020-07-22 12:25:55 +08:00
644612dc7e
Add LB instruction for RV32I
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M-Labs/riscv-formal-nmigen
2020-07-22 12:09:10 +08:00
0f59fbc2d4
Add BGEU instruction for RV32I
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M-Labs/riscv-formal-nmigen
2020-07-22 12:03:48 +08:00
c1196e23c6
Add BLTU instruction for RV32I
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M-Labs/riscv-formal-nmigen
2020-07-22 11:59:40 +08:00
83e859ea27
Add BGE instruction for RV32I
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M-Labs/riscv-formal-nmigen
2020-07-22 11:55:35 +08:00
a6ab3264c7
Add BLT instruction for RV32I
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M-Labs/riscv-formal-nmigen
2020-07-22 11:48:56 +08:00
56005333d3
ADD BNE instruction for RV32I
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M-Labs/riscv-formal-nmigen
2020-07-22 11:40:40 +08:00
013679fbf2
Add BEQ instruction for RV32I
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M-Labs/riscv-formal-nmigen
2020-07-21 17:55:38 +08:00
395f29cf93
Mention expected scope of project in README
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M-Labs/riscv-formal-nmigen
2020-07-21 17:20:45 +08:00
ffb71e0751
Add JALR instruction for RV32I
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M-Labs/riscv-formal-nmigen
2020-07-21 17:03:24 +08:00
9cee89b495
Add JAL instruction for RV32I
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M-Labs/riscv-formal-nmigen
2020-07-21 16:30:42 +08:00
86a33ed533
Add AUIPC instruction for RV32I
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M-Labs/riscv-formal-nmigen
2020-07-21 16:14:14 +08:00
10563f5de9
Add LUI instruction for RV32I
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M-Labs/riscv-formal-nmigen
2020-07-14 10:42:21 +08:00
43f6897e2e
Copy license from source
dsleung
created repository
M-Labs/riscv-formal-nmigen
2020-07-14 10:30:37 +08:00
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