Sebastien Bourdeauducq fcc91513ec drop board-generated on ARTIQ 7 ... This is becoming too complicated, and with the number of systems increasing we should find a better way of managing bitstream builds anyway. Simply caching Verilog->bitfile does not cut it.		2021-09-12 18:35:26 +08:00
artiq-board-generated	s/stdenv.lib/lib/	2021-03-11 17:32:26 +01:00
artiq-fast	drop board-generated on ARTIQ 7	2021-09-12 18:35:26 +08:00
artiq-full	bumped dax version to 6.5	2021-08-30 18:46:45 -04:00
gluelogic	gluelogic: fix 84fc1375d	2021-03-14 17:16:21 +08:00
hydra	drop board-generated on ARTIQ 7	2021-09-12 18:35:26 +08:00
mcu	mcu: fix build	2021-08-09 14:33:17 +08:00
artiq-fast.nix	apply Mozilla nixpkgs overlay more thoroughly	2021-09-12 18:35:03 +08:00
artiq-full.nix	drop board-generated on ARTIQ 7	2021-09-12 18:35:26 +08:00
artiq-zynq.nix	zynq: also run ARTIQ_LOW_LATENCY tests	2021-08-04 10:40:37 +08:00
gluelogic.nix	cpld -> gluelogic	2020-05-31 16:47:30 +08:00
mcu.nix	mcu: missing file rename from 0d706f000f	2021-02-06 22:05:00 +08:00
web.nix	web fixes and improvements	2019-07-19 15:00:06 +08:00
zynq-rs.nix	zynq: stable and beta channels	2021-07-07 18:08:30 +08:00