Commit Graph

88 Commits

Author SHA1 Message Date
9bfc4aae59 hydra: add sipyco job 2022-02-12 11:05:21 +08:00
2f493ab9d3 reorganize artiq hydra settings, rename flake to main-beta 2022-02-12 10:08:57 +08:00
3d0e51171b hydra: move zynq-beta to flake 2022-02-04 17:11:06 +08:00
3df3b7daa0 zynq-rs: move to flakes 2022-01-27 13:09:47 +08:00
0fae14a5ad mcu -> mcu-contrib 2022-01-26 07:48:45 +08:00
5f90f65d59 hydra: add humpback-dds flakes job 2022-01-25 10:13:51 +08:00
a069c0aba3 hydra: use git+https URL for ARTIQ
github: flake URL lacks revCount
2022-01-19 20:02:33 +08:00
778dab71a2 hydra: add thermostat flakes job 2022-01-19 10:36:54 +08:00
436e0d8c88 replace insecure git:// URLs 2022-01-11 09:42:32 +08:00
c0bf6837d9 gluelogic: nixos 21.11 2021-12-01 20:47:34 +08:00
679cd25a68 web: nixos 21.11 2021-12-01 20:46:43 +08:00
e8bb121ece mcu: nixos 21.11 2021-12-01 20:46:08 +08:00
62c16ce859 hydra: fix nac3 flake url 2021-10-08 08:16:57 +08:00
d739286ff5 hydra: build nac3 flake 2021-10-08 00:34:05 +08:00
88b98ac644 hydra: fix full-beta inputs (2) 2021-09-12 18:45:14 +08:00
1754b13b73 hydra: fix full-beta inputs 2021-09-12 18:41:48 +08:00
1899a4f818 hydra: update description for board-generated 2021-09-12 18:38:42 +08:00
fcc91513ec drop board-generated on ARTIQ 7
This is becoming too complicated, and with the number of systems increasing we should
find a better way of managing bitstream builds anyway. Simply caching Verilog->bitfile
does not cut it.
2021-09-12 18:35:26 +08:00
54157028c9 riscv support in beta version (WIP) 2021-09-12 18:17:47 +08:00
108309388e hydra: fix flakes declarative jobset 2021-08-25 13:33:18 +08:00
9d34f0d091 add riscv jobset 2021-08-18 14:24:20 +08:00
5b65a378bf hydra: keep bigger build archive 2021-08-07 12:34:30 +08:00
c9efc20aeb switch everything to nixpkgs 21.05
No problems found during testing and OpenOCD changes make HITL tricky while keeping 20.09.
2021-07-27 10:25:12 +08:00
92d2b24e7c zynq: stable and beta channels 2021-07-07 18:08:30 +08:00
a00537688c mcu: temporarily switch to pre-mqtt branch on harry's fork 2021-07-02 15:58:40 +08:00
8646fd8822 zynq: build with nixos-21.05 2021-06-19 22:58:57 +08:00
b8d4da3004 hydra: use nixos 21.05 for web 2021-06-02 15:13:31 +08:00
e0b1b8576f hydra: use nixos 21.05 for gluelogic 2021-06-02 08:55:25 +08:00
dc1dd6e61c hydra: use nixos 21.05 for mcu 2021-06-02 08:46:17 +08:00
ac7b8b4029 hydra: use nixos 20.09 for ARTIQ legacy 2021-06-02 08:24:14 +08:00
69ba4229d2 hydra: use nixos 21.05 for ARTIQ beta 2021-06-02 08:17:19 +08:00
79cb6fdcf7 hydra: fix case in previous commit 2021-05-13 15:42:22 +08:00
5bd75bcbd2 hydra: add data required by new GiteaStatus plugin 2021-05-13 15:41:46 +08:00
a57b927418 targets -> boards 2021-02-17 16:25:18 +08:00
5b2ee17cb9 build Zynq targets against ARTIQ stable 2021-02-17 16:21:51 +08:00
c46534d41b ARTIQ-6 is now stable, add legacy builds 2021-02-17 16:13:09 +08:00
5eea3a8267 beta -> a6p 2021-02-17 16:01:19 +08:00
9806228a8c check artiq-board-generated more often 2021-02-16 10:01:10 +08:00
64ee51b673 artiq-full: split code generation into artiq-board-generated jobset 2021-02-15 04:15:09 +01:00
87c2586250 mcu: add Hydra Git input for Sayma MMC firmware 2021-02-06 22:03:13 +08:00
0d706f000f stm32 -> mcu 2021-02-06 21:45:40 +08:00
eac7f4bddb Revert "artiq: move stable to nixpkgs 20.09"
This reverts commit b810407aa9.
2021-01-28 12:21:09 +08:00
b810407aa9 artiq: move stable to nixpkgs 20.09 2021-01-27 13:14:12 +08:00
59844c28d9 zynq: build with nixos 20.09 2020-10-13 18:24:57 +08:00
4172f745e3 add Phaser gateware 2020-10-12 22:49:47 +08:00
a9108d5fa3 stm32: move to nixos 20.09 2020-10-08 14:43:22 +08:00
9754f45904 use new simplified hydra jobset declarations 2020-10-08 14:08:20 +08:00
59ad8b124a remove HeavyX 2020-10-08 14:00:18 +08:00
1263c7f15f Revert "attempting to fix hydra jobsets"
This reverts commit 477f9ce197.
2020-10-08 13:54:36 +08:00
477f9ce197 attempting to fix hydra jobsets 2020-10-08 13:52:17 +08:00