diff --git a/nac3artiq/src/lib.rs b/nac3artiq/src/lib.rs
index 5ef11904..fb71ee89 100644
--- a/nac3artiq/src/lib.rs
+++ b/nac3artiq/src/lib.rs
@@ -212,7 +212,7 @@ impl Nac3 {
         };
         let time_fns: &(dyn TimeFns + Sync) = match isa {
             Isa::Host => &timeline::EXTERN_TIME_FNS,
-            Isa::RiscV32G => &timeline::NOW_PINNING_TIME_FNS,
+            Isa::RiscV32G => &timeline::NOW_PINNING_TIME_FNS_64,
             Isa::RiscV32IMA => &timeline::NOW_PINNING_TIME_FNS,
             Isa::CortexA9 => &timeline::EXTERN_TIME_FNS,
         };
diff --git a/nac3artiq/src/timeline.rs b/nac3artiq/src/timeline.rs
index b2a6f116..e676793b 100644
--- a/nac3artiq/src/timeline.rs
+++ b/nac3artiq/src/timeline.rs
@@ -7,6 +7,26 @@ pub trait TimeFns {
     fn emit_delay_mu<'ctx, 'a>(&self, ctx: &mut CodeGenContext<'ctx, 'a>, dt: BasicValueEnum<'ctx>);
 }
 
+pub struct NowPinningTimeFns64 {}
+
+// For FPGA design reasons, on VexRiscv with 64-bit data bus, the "now" CSR is split into two 32-bit
+// values that are each padded to 64-bits.
+impl TimeFns for NowPinningTimeFns64 {
+    fn emit_now_mu<'ctx, 'a>(&self, ctx: &mut CodeGenContext<'ctx, 'a>) -> BasicValueEnum<'ctx> {
+        unimplemented!();
+    }
+
+    fn emit_at_mu<'ctx, 'a>(&self, ctx: &mut CodeGenContext<'ctx, 'a>, t: BasicValueEnum<'ctx>) {
+        unimplemented!();
+    }
+
+    fn emit_delay_mu<'ctx, 'a>(&self, ctx: &mut CodeGenContext<'ctx, 'a>, dt: BasicValueEnum<'ctx>) {
+        unimplemented!();
+    }
+}
+
+pub static NOW_PINNING_TIME_FNS_64: NowPinningTimeFns64 = NowPinningTimeFns64 {};
+
 pub struct NowPinningTimeFns {}
 
 impl TimeFns for NowPinningTimeFns {