From 7ab2114882b46de47b7cb3fbaee4c8cc3f0f2847 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 24 Sep 2021 14:45:01 +0800 Subject: [PATCH] nac3embedded: switch to Zynq (#24) --- nac3embedded/device_db.py | 11 +++++++---- nac3embedded/src/lib.rs | 8 ++++++-- 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/nac3embedded/device_db.py b/nac3embedded/device_db.py index abf1cab0..558af7d5 100644 --- a/nac3embedded/device_db.py +++ b/nac3embedded/device_db.py @@ -1,13 +1,16 @@ # python demo.py # artiq_run module.elf -core_addr = "192.168.1.50" - device_db = { "core": { "type": "local", "module": "artiq.coredevice.core", "class": "Core", - "arguments": {"host": core_addr, "ref_period": 1e-9} - } + "arguments": { + "host": "192.168.1.52", + "ref_period": 1e-9, + "ref_multiplier": 8, + "target": "cortexa9" + } + }, } diff --git a/nac3embedded/src/lib.rs b/nac3embedded/src/lib.rs index e63f6391..d00c903e 100644 --- a/nac3embedded/src/lib.rs +++ b/nac3embedded/src/lib.rs @@ -147,14 +147,18 @@ impl Nac3 { builder.populate_module_pass_manager(&passes); passes.run_on(module); - let triple = TargetTriple::create("riscv32-unknown-linux"); + // For RISC-V (needs https://git.m-labs.hk/M-Labs/nac3/issues/24) + //let triple = TargetTriple::create("riscv32-unknown-linux"); + //let features = "+a,+m"; + let triple = TargetTriple::create("armv7-unknown-linux-gnueabihf"); + let features = "+dsp,+fp16,+neon,+vfp3"; let target = Target::from_triple(&triple).expect("couldn't create target from target triple"); let target_machine = target .create_target_machine( &triple, "", - "+a,+m", + features, OptimizationLevel::Default, RelocMode::PIC, CodeModel::Default,