forked from M-Labs/nac3
artiq: Specify target CPU when creating LLVM target options
We can try to optimize for the host and Cortex-A9 chips; The RISC-V ISAs do not target specific chips, so we will fallback to using the generic CPU.
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@ -677,6 +677,15 @@ impl Nac3 {
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}
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}
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/// Returns the [String] representing the target CPU used for compiling to [isa].
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fn get_llvm_target_cpu(isa: Isa) -> String {
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match isa {
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Isa::Host => TargetMachine::get_host_cpu_name().to_string(),
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Isa::RiscV32G | Isa::RiscV32IMA => "generic-rv32".to_string(),
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Isa::CortexA9 => "cortex-a9".to_string(),
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}
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}
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/// Returns the [String] representing the target features used for compiling to [isa].
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fn get_llvm_target_features(isa: Isa) -> String {
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match isa {
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@ -692,7 +701,7 @@ impl Nac3 {
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fn get_llvm_target_options(isa: Isa) -> CodeGenTargetMachineOptions {
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CodeGenTargetMachineOptions {
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triple: Nac3::get_llvm_target_triple(isa).as_str().to_string_lossy().into_owned(),
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cpu: String::default(),
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cpu: Nac3::get_llvm_target_cpu(isa),
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features: Nac3::get_llvm_target_features(isa),
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reloc_mode: RelocMode::PIC,
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..CodeGenTargetMachineOptions::from_host()
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