forked from M-Labs/artiq-zynq
set up PL clocks
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parent
e750b61973
commit
a8de572014
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@ -15,7 +15,7 @@ let
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version = "0.1.0";
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src = ./src;
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cargoSha256 = "064s5kg0hw27vibh2nih7rkg1iw7k4jkrjw41xx0dyqk4z8fy3q8";
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cargoSha256 = "0xminds5fyp7c9vsx651zv3yzyhxnl9a02rhjl2wfxf8m679r45l";
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nativeBuildInputs = [
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pkgs.gnumake
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@ -200,7 +200,7 @@ dependencies = [
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[[package]]
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name = "libasync"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#e67efe439b4c1a535a9d784fef3547d95584a909"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#371e59cef57746e3dd4cae915be7fd3286972822"
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dependencies = [
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"embedded-hal",
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"libcortex_a9",
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@ -212,7 +212,7 @@ dependencies = [
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[[package]]
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name = "libboard_zynq"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#e67efe439b4c1a535a9d784fef3547d95584a909"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#371e59cef57746e3dd4cae915be7fd3286972822"
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dependencies = [
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"bit_field",
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"embedded-hal",
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@ -236,7 +236,7 @@ dependencies = [
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[[package]]
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name = "libcortex_a9"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#e67efe439b4c1a535a9d784fef3547d95584a909"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#371e59cef57746e3dd4cae915be7fd3286972822"
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dependencies = [
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"bit_field",
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"libregister",
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@ -245,7 +245,7 @@ dependencies = [
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[[package]]
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name = "libregister"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#e67efe439b4c1a535a9d784fef3547d95584a909"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#371e59cef57746e3dd4cae915be7fd3286972822"
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dependencies = [
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"bit_field",
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"vcell",
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@ -255,7 +255,7 @@ dependencies = [
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[[package]]
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name = "libsupport_zynq"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#e67efe439b4c1a535a9d784fef3547d95584a909"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#371e59cef57746e3dd4cae915be7fd3286972822"
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dependencies = [
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"compiler_builtins",
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"libboard_zynq",
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@ -396,6 +396,7 @@ dependencies = [
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"libboard_zynq",
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"libc",
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"libcortex_a9",
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"libregister",
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"libsupport_zynq",
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"log",
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"num-derive",
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@ -23,6 +23,7 @@ libboard_zynq = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
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libsupport_zynq = { default-features = false, git = "https://git.m-labs.hk/M-Labs/zc706.git" }
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libcortex_a9 = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
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libasync = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
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libregister = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
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dyld = { path = "../libdyld" }
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dwarf = { path = "../libdwarf" }
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unwind = { path = "../libunwind" }
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@ -11,6 +11,7 @@ use log::info;
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use libboard_zynq::{timer::GlobalTimer, logger, devc, slcr};
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use libsupport_zynq::ram;
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use libregister::RegisterW;
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mod sd_reader;
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mod config;
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@ -50,6 +51,26 @@ pub fn main_core0() {
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ram::init_alloc_linker();
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// Set up PS->PL clocks
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slcr::RegisterBlock::unlocked(|slcr| {
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// As we are touching the mux, the clock may glitch, so reset the PL.
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slcr.fpga_rst_ctrl.write(
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slcr::FpgaRstCtrl::zeroed()
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.fpga0_out_rst(true)
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.fpga1_out_rst(true)
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.fpga2_out_rst(true)
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.fpga3_out_rst(true)
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);
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slcr.fpga0_clk_ctrl.write(
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slcr::Fpga0ClkCtrl::zeroed()
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.src_sel(slcr::PllSource::IoPll)
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.divisor0(8)
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.divisor1(1)
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);
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slcr.fpga_rst_ctrl.write(
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slcr::FpgaRstCtrl::zeroed()
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);
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});
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if devc::DevC::new().is_done() {
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info!("gateware already loaded");
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// Do not load again: assume that the gateware already present is
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