From 59cf2764ce7a9b04d1f2784415fe0447b24a189c Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Tue, 21 Jul 2020 12:47:20 +0800
Subject: [PATCH] dma: report AXI bus error

---
 src/gateware/dma.py | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/src/gateware/dma.py b/src/gateware/dma.py
index ef0555e1..e014fab6 100644
--- a/src/gateware/dma.py
+++ b/src/gateware/dma.py
@@ -12,7 +12,7 @@ import endianness
 AXI_BURST_LEN = 16
 
 
-class AXIReader(Module):
+class AXIReader(Module, AutoCSR):
     def __init__(self, membus):
         aw = len(membus.ar.addr)
         dw = len(membus.r.data)
@@ -20,6 +20,8 @@ class AXIReader(Module):
         self.sink = stream.Endpoint([("address", aw - alignment_bits)])
         self.source = stream.Endpoint([("data", dw)])
 
+        self.bus_error = CSRStatus()
+
         # # #
 
         eop_pending = Signal()
@@ -57,6 +59,17 @@ class AXIReader(Module):
             self.source.eop.eq(eop_pending & membus.r.last & (inflight_cnt == 1))
         ]
 
+        stopped = Signal(reset=1)
+        self.sync += [
+            If(self.source.stb & self.source.ack & self.source.eop, stopped.eq(1)),
+            If(self.sink.stb & self.sink.ack, stopped.eq(0)),
+            If(stopped & (self.sink.stb & self.sink.ack),
+                # reset bus error status on new run
+                self.bus_error.status.eq(0)),
+            If(membus.r.valid & membus.r.valid & (membus.r.resp != axi.Response.okay),
+                self.bus_error.status.eq(1))
+        ]
+
 
 class DMAReader(Module, AutoCSR):
     def __init__(self, membus, enable):