dpn
/
artiq-zynq
forked from M-Labs/artiq-zynq
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

drtio: port 64-bit padding from mainline

This commit is contained in:
mwojcik 2022-05-24 15:43:01 +08:00
parent efc432352e
commit 57d7f01b04
2 changed files with 8 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/libboard_artiq/src/drtioaux.rs
View File

@ -153,12 +153,11 @@ pub fn send(linkno: u8, packet: &Packet) -> Result<(), Error> {
packet.write_to(&mut writer)?;
let padding = 4 - (writer.position() % 4);
if padding != 4 {
// Pad till offset 4, insert checksum there
let padding = (12 - (writer.position() % 8)) % 8;
for _ in 0..padding {
writer.write_u8(0)?;
}
}
let checksum = crc::crc32::checksum_ieee(&writer.get_ref()[0..writer.position()]);
writer.write_u32(checksum)?;

5
src/libboard_artiq/src/drtioaux_async.rs
View File

@ -124,12 +124,11 @@ pub async fn send(linkno: u8, packet: &Packet) -> Result<(), Error> {
packet.write_to(&mut writer)?;
let padding = 4 - (writer.position() % 4);
if padding != 4 {
// Pad till offset 4, insert checksum there
let padding = (12 - (writer.position() % 8)) % 8;
for _ in 0..padding {
writer.write_u8(0)?;
}
}
let checksum = crc::crc32::checksum_ieee(&writer.get_ref()[0..writer.position()]);
writer.write_u32(checksum)?;