forked from M-Labs/artiq-zynq
kernel: refactor main_core1 into KernelImage
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b3d4590eec
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2c1773b91b
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@ -1,11 +1,12 @@
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//! Kernel prologue/epilogue that runs on the 2nd CPU core
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use core::{ptr, mem};
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use core::{mem, ptr};
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use alloc::borrow::ToOwned;
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use log::{debug, info, error};
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use cslice::CSlice;
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use libcortex_a9::{enable_fpu, cache::dcci_slice, sync_channel};
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use dyld;
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use dyld::{self, Library};
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use crate::eh_artiq;
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use super::{
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api::resolve,
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@ -56,7 +57,50 @@ unsafe fn attribute_writeback(typeinfo: *const ()) {
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}
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}
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}
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struct KernelImage {
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library: Library,
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__modinit__: u32,
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typeinfo: Option<u32>,
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}
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impl KernelImage {
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pub fn new(library: Library) -> Result<Self, dyld::Error> {
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let __modinit__ = library.lookup(b"__modinit__")
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.ok_or(dyld::Error::Lookup("__modinit__".to_owned()))?;
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let typeinfo = library.lookup(b"typeinfo");
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// clear .bss
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let bss_start = library.lookup(b"__bss_start");
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let end = library.lookup(b"_end");
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if let Some(bss_start) = bss_start {
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let end = end
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.ok_or(dyld::Error::Lookup("_end".to_owned()))?;
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unsafe {
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ptr::write_bytes(bss_start as *mut u8, 0, (end - bss_start) as usize);
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}
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}
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Ok(KernelImage {
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library,
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__modinit__,
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typeinfo,
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})
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}
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pub unsafe fn exec(&mut self) {
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// Flush data cache entries for the image in DDR, including
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// Memory/Instruction Symchronization Barriers
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dcci_slice(self.library.image.data);
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(mem::transmute::<u32, fn()>(self.__modinit__))();
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if let Some(typeinfo) = self.typeinfo {
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attribute_writeback(typeinfo as *const ());
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}
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}
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}
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#[no_mangle]
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pub fn main_core1() {
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debug!("Core1 started");
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@ -76,36 +120,22 @@ pub fn main_core1() {
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}
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let mut core1_rx = core1_rx.unwrap();
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let mut current_modinit: Option<u32> = None;
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let mut current_typeinfo: Option<u32> = None;
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let mut library_handle: Option<dyld::Library> = None;
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// set on load, cleared on start
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let mut loaded_kernel = None;
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loop {
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let message = core1_rx.recv();
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match *message {
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Message::LoadRequest(data) => {
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match dyld::load(&data, &resolve) {
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Ok(library) => {
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let result = dyld::load(&data, &resolve)
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.and_then(KernelImage::new);
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match result {
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Ok(kernel) => {
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unsafe {
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KERNEL_LOAD_ADDR = library.image.as_ptr() as usize;
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KERNEL_LOAD_ADDR = kernel.library.image.as_ptr() as usize;
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}
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let bss_start = library.lookup(b"__bss_start");
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let end = library.lookup(b"_end");
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if let Some(bss_start) = bss_start {
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let end = end.unwrap();
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unsafe {
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ptr::write_bytes(bss_start as *mut u8, 0, (end - bss_start) as usize);
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}
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}
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let __modinit__ = library.lookup(b"__modinit__").unwrap();
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current_modinit = Some(__modinit__);
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current_typeinfo = library.lookup(b"typeinfo");
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loaded_kernel = Some(kernel);
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debug!("kernel loaded");
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// Flush data cache entries for the image in DDR, including
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// Memory/Instruction Symchronization Barriers
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dcci_slice(library.image.data);
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core1_tx.send(Message::LoadCompleted);
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library_handle = Some(library);
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},
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Err(error) => {
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error!("failed to load shared library: {}", error);
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@ -115,19 +145,15 @@ pub fn main_core1() {
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},
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Message::StartRequest => {
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info!("kernel starting");
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if let Some(__modinit__) = current_modinit {
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if let Some(mut kernel) = loaded_kernel.take() {
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unsafe {
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KERNEL_CHANNEL_0TO1 = mem::transmute(&mut core1_rx);
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KERNEL_CHANNEL_1TO0 = mem::transmute(&mut core1_tx);
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(mem::transmute::<u32, fn()>(__modinit__))();
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if let Some(typeinfo) = current_typeinfo {
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attribute_writeback(typeinfo as *const ());
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}
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kernel.exec();
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KERNEL_CHANNEL_0TO1 = ptr::null_mut();
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KERNEL_CHANNEL_1TO0 = ptr::null_mut();
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}
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}
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library_handle = None;
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info!("kernel finished");
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core1_tx.send(Message::KernelFinished);
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}
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