forked from M-Labs/artiq-zynq
analyzer: fix endianness issue
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84630d66e3
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10a12245a3
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@ -7,6 +7,15 @@ from migen_axi.interconnect import axi
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from artiq.gateware.rtio.analyzer import message_len, MessageEncoder
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def convert_endianness(signal):
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assert len(signal) % 8 == 0
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nbytes = len(signal)//8
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signal_bytes = []
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for i in range(nbytes):
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signal_bytes.append(signal[8*i:8*(i+1)])
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return Cat(*reversed(signal_bytes))
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class AXIDMAWriter(Module, AutoCSR):
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def __init__(self, membus, max_outstanding_requests):
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aw = len(membus.aw.addr)
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@ -55,7 +64,7 @@ class AXIDMAWriter(Module, AutoCSR):
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membus.w.id.eq(0),
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membus.w.valid.eq(self.sink.stb),
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self.sink.ack.eq(membus.w.ready),
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membus.w.data.eq(self.sink.data),
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membus.w.data.eq(convert_endianness(self.sink.data)),
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membus.w.strb.eq(2**(dw//8)-1),
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]
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beat_count = Signal(max=burst_length)
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