forked from M-Labs/artiq-zynq
analyzer: drive wid and wstrb
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@ -52,9 +52,11 @@ class AXIDMAWriter(Module, AutoCSR):
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]
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]
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self.comb += [
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self.comb += [
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membus.w.id.eq(0),
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membus.w.valid.eq(self.sink.stb),
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membus.w.valid.eq(self.sink.stb),
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self.sink.ack.eq(membus.w.ready),
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self.sink.ack.eq(membus.w.ready),
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membus.w.data.eq(self.sink.data)
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membus.w.data.eq(self.sink.data),
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membus.w.strb.eq(2**(dw//8)-1),
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]
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]
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beat_count = Signal(max=burst_length)
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beat_count = Signal(max=burst_length)
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self.sync += [
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self.sync += [
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