forked from sinara-hw/assembly
157 lines
7.6 KiB
Markdown
157 lines
7.6 KiB
Markdown
# Sinara 4456 synthesizer Mirny / Sinara 4457 Almazny Mezzanine card
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* [Wiki Mirny](https://github.com/sinara-hw/mirny/wiki)
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* [Wiki Almazny](https://github.com/sinara-hw/Almazny/wiki)
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## JSON
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```json
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{
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"type": "mirny",
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"almazny": true, // for mirny with almazny only
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"ports": [<port num>],
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"clk_sel": 2, // optional
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"refclk": 125e6 // optional
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}
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```
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## Getting the firmware
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Here is [Mirny 0.3.1 firmware](../extra/mirny/mirny-0.3.1.zip). It contains a single ``.jed`` file that can be flashed following [flashing instructions](#flashing). This firmware supports Almazny v1.2+.
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If you are using a legacy Almazny (v1.0-1.1), due to different signals routed, you need to flash the older [0.2.4 firmware with Almazny support](../extra/mirny/mirny_0.2.4_legacy_almazny.zip).
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### Building firmware (optional)
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However, if you need to make chances or build from source, follow these instructions.
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Once you get your hands on the firmware source code, you will need to work around few shortcomings of Nix, mainly not being able to run dynamically linked executables.
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You will need:
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- Xilinx ISE 14.7 installed on your system (this guide is assuming ``/opt/Xilinx`` path),
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- an environment with Migen.
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One way to do it is to create an FHS environment, like ARTIQ does for Vivado, within ARTIQ's ``flake.nix`` (to leverage Migen already being there), by adding these lines:
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```
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iseEnv = pkgs.buildFHSEnv {
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name = "ise-env";
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targetPkgs = vivadoDeps;
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};
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ise = pkgs.buildFHSEnv {
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name = "ise";
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targetPkgs = vivadoDeps;
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profile = "set -e; source /opt/Xilinx/14.7/ISE_DS/settings64.sh";
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runScript = "ise";
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};
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```
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Add them below ``vivadoEnv``. Then add ``iseEnv`` and ``ise`` to the dev shell's build inputs. Call ``nix develop`` on that.
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Then you can build Mirny:
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```shell
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nix develop
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ise-env
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cd ../mirny # or wherever your source is at
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source /opt/Xilinx/14.7/ISE_DS/settings64.sh
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python mirny_impl.py
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```
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### Flashing
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For flashing, you will need Xilinx ISE 14.7 installed on your system (here assuming ``/opt/Xilinx`` path), and ``xc3sprog`` with the appropriate HS2 JTAG adapter.
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```shell
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nix-shell -p xc3sprog
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xc3sprog -c jtaghs2 -m /opt/Xilinx/14.7/ISE_DS/ISE/xbr/data -v build/mirny.jed
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```
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## Testing
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### Without Almazny
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```text
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*** Testing Mirny PLLs.
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Initializing CPLDs...
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mirny0_cpld...
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...done
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All mirny channels active.
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Frequencies:
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mirny0_ch0 1000MHz
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mirny0_ch0 info: {'f_outA': 1000000000.0, 'f_outB': 8000000000, 'output_divider': 4, 'f_vco': 4000000000, 'pll_n': 40, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
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mirny0_ch1 1100MHz
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mirny0_ch1 info: {'f_outA': 1100000000.0, 'f_outB': 8800000000, 'output_divider': 4, 'f_vco': 4400000000, 'pll_n': 44, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
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mirny0_ch2 1200MHz
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mirny0_ch2 info: {'f_outA': 1200000000.0, 'f_outB': 9600000000, 'output_divider': 4, 'f_vco': 4800000000, 'pll_n': 48, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
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mirny0_ch3 1300MHz
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mirny0_ch3 info: {'f_outA': 1300000000.0, 'f_outB': 10400000000, 'output_divider': 4, 'f_vco': 5200000000, 'pll_n': 52, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
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```
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After running `artiq_sinara_test`:
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1. Install gqrx `nix-shell -p gqrx`
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2. Connect HackRF One via USB cable only
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3. Run gqrx and choose `HackRF HackRF One...`
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4. Default settings
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5. When gqrx loaded, start DSP processing with frequency at mirnyN_chM freq
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6. Connect the probe through attenuator to the Mirny's port
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7. You should see significant signal emission on choosen freq compared to nearby freqs (see image below)
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8. Repeat 5-7 for every channel
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### With Almazny (ARTIQ 7)
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At first, `artiq_sinara_test` will prompt you for testing Mirnies as the would be without Almazny.
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After that, it will prompt you with testing the Almazny:
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```text
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*** Testing Almaznys.
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mirny1_almazny...
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Initializing Mirny CPLDs...
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mirny0_cpld...
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mirny1_cpld...
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...done
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Testing attenuators. Frequencies:
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mirny0_ch0 4000MHz
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mirny0_ch0 info: {'f_outA': 2000000000.0, 'f_outB': 8000000000, 'output_divider': 2, 'f_vco': 4000000000, 'pll_n': 40, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
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mirny0_ch1 4100MHz
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mirny0_ch1 info: {'f_outA': 2050000000.0, 'f_outB': 8200000000, 'output_divider': 2, 'f_vco': 4100000000, 'pll_n': 41, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
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mirny0_ch2 4200MHz
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mirny0_ch2 info: {'f_outA': 2100000000.0, 'f_outB': 8400000000, 'output_divider': 2, 'f_vco': 4200000000, 'pll_n': 42, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
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mirny0_ch3 4300MHz
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mirny0_ch3 info: {'f_outA': 2150000000.0, 'f_outB': 8600000000, 'output_divider': 2, 'f_vco': 4300000000, 'pll_n': 43, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
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mirny1_ch0 4500MHz
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mirny1_ch0 info: {'f_outA': 2250000000.0, 'f_outB': 9000000000, 'output_divider': 2, 'f_vco': 4500000000, 'pll_n': 45, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
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mirny1_ch1 4600MHz
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mirny1_ch1 info: {'f_outA': 2300000000.0, 'f_outB': 9200000000, 'output_divider': 2, 'f_vco': 4600000000, 'pll_n': 46, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
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mirny1_ch2 4700MHz
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mirny1_ch2 info: {'f_outA': 2350000000.0, 'f_outB': 9400000000, 'output_divider': 2, 'f_vco': 4700000000, 'pll_n': 47, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
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mirny1_ch3 4800MHz
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mirny1_ch3 info: {'f_outA': 2400000000.0, 'f_outB': 9600000000, 'output_divider': 2, 'f_vco': 4800000000, 'pll_n': 48, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
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RF ON, all attenuators ON. Press ENTER when done.
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RF ON, half power attenuators ON. Press ENTER when done.
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RF ON, all attenuators OFF. Press ENTER when done.
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SR outputs are OFF. Press ENTER when done.
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RF ON, all attenuators are ON. Press ENTER when done.
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RF OFF. Press ENTER when done.
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```
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Similar to _Without Almazny_, check mirnies' channels emissions on defined frequencies.
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You should also see differences in various modes, but that may require disabling the gain.
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### Tips
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~~Mirnies often fail `ValueError: MUXOUT not high`, in that case restart the tests or reboot the board(s).~~ - fixed in [9569cfb](https://github.com/m-labs/artiq/commit/9569cfb26329c0acdc1705d3256d2506b7bccce5)
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For Almazny v1.0 and 1.1 support, CPLD firmware 0.2.4 (linked above) must be flashed onto Mirny.
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For Almazny v1.2+ support, CPLD firmware 0.3.1+ (with fixes) must be flashed onto Mirny. |