Add mismatch problem to the urukul and add known issue to the kasli-soc

Signed-off-by: Egor Savkin <es@m-labs.hk>

src/build_test_firmware.md

@@ -61,6 +61,11 @@ artiq_coremgmt config write -f boot result/boot.bin
 artiq_sinara_tester
 ```
 
+### Known issues
+
+* [artiq-zynq#197](https://git.m-labs.hk/M-Labs/artiq-zynq/issues/197) - some cards (Sampler, Mirny, Zotino and others)  
+  do not work properly with some EEM ports. You might need to reconnect the card to the other ports until it gets working.
+
 ## Master-satellite setups
 
 1. Change `base` in JSON to the respective `master` or `satellite`, add `"enable_sata_drtio": true` if needed to the master,

src/hw/urukul.md

@@ -9,7 +9,7 @@
 {
     "type": "urukul",
     "dds": "<variant>", // ad9910/ad9912
-    "ports": [<port num>, <port num>],
+    "ports": [<port num>, <port num>], // second port is optional
     "clk_sel": <clock num>,
     "refclk": <freq>, // for external clock signal
     "pll_en": <0 or 1, default 1> // PLL bypass, to allow higher external clocker frequencies (1e9 for example)
@@ -112,4 +112,12 @@ ValueError: PLL lock timeout
 
 This can happen due to lack/bad clock source connection. Check that clock source is connected respective to the customer needs,
 and if it is connected to the [Clocker](clocker.md), check that clocker receives clock signal properly and `EXT`/`INT` pin 
-matches real clocker source.
+matches real clocker source.
+
+### Urukul AD9910 AUX_DAC mismatch
+
+```pycon
+ValueError: Urukul AD9910 AUX_DAC mismatch
+```
+
+Ensure it is the AD9910 and not the AD9912.