From 48b85eac93cad9183df969d243354f23c010e946 Mon Sep 17 00:00:00 2001 From: Egor Savkin Date: Wed, 15 Nov 2023 15:09:47 +0800 Subject: [PATCH] Fix formatting Signed-off-by: Egor Savkin --- src/sw_sup/clocking.md | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/sw_sup/clocking.md b/src/sw_sup/clocking.md index 069d729..0b55cfd 100644 --- a/src/sw_sup/clocking.md +++ b/src/sw_sup/clocking.md @@ -3,8 +3,7 @@ This page describes ways to set up clocking. Official documentation references: * [Carrier configuration](https://m-labs.hk/artiq/manual/installing.html#miscellaneous-configuration-of-the-core-device) -* -Devices' [available options](https://m-labs.hk/artiq/manual/core_drivers_reference.html), [Urukul example](https://m-labs.hk/artiq/manual/core_drivers_reference.html#artiq.coredevice.urukul.CPLD) +* Devices' [available options](https://m-labs.hk/artiq/manual/core_drivers_reference.html), [Urukul example](https://m-labs.hk/artiq/manual/core_drivers_reference.html#artiq.coredevice.urukul.CPLD) In general, any RF card and Carriers require some clock source. Most of them have both internal clock signal generator and external MMCX and/or SMA connectors to accept the signal. By default the internal clock is used for Carriers, @@ -60,7 +59,11 @@ so Urukul entry may look like this: ```json { - "type": "urukul", "dds": "ad9910", "ports": [1, 2], "refclk": 10e6, "clk_sel": 1 + "type": "urukul", + "dds": "ad9910", + "ports": [1, 2], + "refclk": 10e6, + "clk_sel": 1 } ```