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3 Commits

Author SHA1 Message Date
f1ee3a7584 rustfmt 2023-05-30 12:22:46 +08:00
165b1400ab flake: update dependencies 2023-05-30 12:10:28 +08:00
63594d7e3d update configuration of IBUFDS_GTE2
Input clock is terminated internally with 50 Ohm on each leg and to 4/5 MGTAVCC.
2023-05-30 12:08:41 +08:00
4 changed files with 24 additions and 20 deletions

22
flake.lock generated
View File

@ -11,11 +11,11 @@
"src-pythonparser": "src-pythonparser"
},
"locked": {
"lastModified": 1685181798,
"narHash": "sha256-pUxlwhxoIMfMkgbVJe3DFBjR5v784RGzfNdBtRKsuy4=",
"lastModified": 1685418630,
"narHash": "sha256-Sbt2LoIBy01ttHmHsgwMgTLFoV9fgKrYL8RpE4hykog=",
"ref": "refs/heads/master",
"rev": "ef2cc2cc125f0aa5fe6e92d87865b0b0bf1dae4c",
"revCount": 8365,
"rev": "0941d3a29a61d250ff02ddfafefd2c9e8c9350e3",
"revCount": 8368,
"type": "git",
"url": "https://github.com/m-labs/artiq.git"
},
@ -115,11 +115,11 @@
},
"nixpkgs": {
"locked": {
"lastModified": 1685004253,
"narHash": "sha256-AbVL1nN/TDicUQ5wXZ8xdLERxz/eJr7+o8lqkIOVuaE=",
"lastModified": 1685356226,
"narHash": "sha256-f2clSOdqi0SvY1WSgbnl2YgCZmoCXOxeUjYeXp8p2zI=",
"owner": "NixOS",
"repo": "nixpkgs",
"rev": "3e01645c40b92d29f3ae76344a6d654986a91a91",
"rev": "0f7f5ca1cdec8dea85bb4fa60378258171d019ad",
"type": "github"
},
"original": {
@ -176,11 +176,11 @@
"src-misoc": {
"flake": false,
"locked": {
"lastModified": 1685174995,
"narHash": "sha256-90UwWt9/TAaFAoYDpiIzHXqMWYfftlps8sodv/Gf07c=",
"lastModified": 1685415268,
"narHash": "sha256-g4+yeSV+HtWjcllM5wk4vNBUVCXtDOzUSKhxXPT7Fyc=",
"ref": "refs/heads/master",
"rev": "d83499b318e8ef021b12e2df261707a165eb3afa",
"revCount": 2439,
"rev": "6d48ce77b6746d3226a682790fbc95b90340986e",
"revCount": 2440,
"submodules": true,
"type": "git",
"url": "https://github.com/m-labs/misoc.git"

View File

@ -71,9 +71,12 @@ class GTP125BootstrapClock(Module):
platform.add_period_constraint(bootstrap_125.p, 8.0)
self.specials += [
Instance("IBUFDS_GTE2",
p_CLKSWING_CFG="0b11",
i_CEB=0,
i_I=bootstrap_125.p, i_IB=bootstrap_125.n, o_O=bootstrap_se),
i_I=bootstrap_125.p, i_IB=bootstrap_125.n,
o_O=bootstrap_se,
p_CLKCM_CFG="TRUE",
p_CLKRCV_TRST="TRUE",
p_CLKSWING_CFG=3),
Instance("BUFG", i_I=bootstrap_se, o_O=self.cd_bootstrap.clk)
]

View File

@ -149,9 +149,9 @@ class ZC706(SoCCore):
i_CEB=0,
i_I=si5324_out.p, i_IB=si5324_out.n,
o_O=cdr_clk,
p_CLKCM_CFG="0b1",
p_CLKRCV_TRST="0b1",
p_CLKSWING_CFG="0b11"),
p_CLKCM_CFG="TRUE",
p_CLKRCV_TRST="TRUE",
p_CLKSWING_CFG=3),
Instance("BUFG", i_I=cdr_clk, o_O=cdr_clk_buf)
]
self.rustc_cfg["has_si5324"] = None

View File

@ -1,4 +1,5 @@
use core::cmp::min;
use libboard_artiq::{drtioaux_proto::ANALYZER_MAX_SIZE, pl::csr};
use libcortex_a9::cache;
@ -35,7 +36,7 @@ pub struct Analyzer {
// necessary for keeping track of sent data
data_len: usize,
sent_bytes: usize,
data_pointer: usize
data_pointer: usize,
}
pub struct Header {
@ -62,7 +63,7 @@ impl Analyzer {
Analyzer {
data_len: 0,
sent_bytes: 0,
data_pointer: 0
data_pointer: 0,
}
}
@ -106,8 +107,8 @@ impl Analyzer {
let last = self.sent_bytes + len == self.data_len;
if i + len >= BUFFER_SIZE {
data_slice[..(BUFFER_SIZE-i)].clone_from_slice(&data[i..BUFFER_SIZE]);
data_slice[(BUFFER_SIZE-i)..len].clone_from_slice(&data[..(i + len) % BUFFER_SIZE]);
data_slice[..(BUFFER_SIZE - i)].clone_from_slice(&data[i..BUFFER_SIZE]);
data_slice[(BUFFER_SIZE - i)..len].clone_from_slice(&data[..(i + len) % BUFFER_SIZE]);
} else {
data_slice[..len].clone_from_slice(&data[i..i + len]);
}