den512
/
artiq-zynq
forked from M-Labs/artiq-zynq
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

runtime: init the logger

This commit is contained in:
Astro 2020-04-22 01:03:58 +02:00 committed by Sebastien Bourdeauducq
parent 4c8653cca4
commit 9dfddd60c5
3 changed files with 6 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Cargo.lock generated
View File

@ -45,9 +45,6 @@ checksum = "0f8cb7306107e4b10e64994de6d3274bd08996a7c1322a27b86482392f96be0a"
[[package]] [[package]]
name = "dyld" name = "dyld"
version = "0.1.0" version = "0.1.0"
dependencies = [
"libboard_zynq",
]
[[package]] [[package]]
name = "libasync" name = "libasync"
@ -185,6 +182,7 @@ dependencies = [
"libboard_zynq", "libboard_zynq",
"libcortex_a9", "libcortex_a9",
"libsupport_zynq", "libsupport_zynq",
"log",
"num-derive", "num-derive",
"num-traits", "num-traits",
] ]

1
runtime/Cargo.toml
View File

@ -13,6 +13,7 @@ default = ["target_zc706"]
num-traits = { version = "0.2", default-features = false } num-traits = { version = "0.2", default-features = false }
num-derive = "0.3" num-derive = "0.3"
cslice = "0.3" cslice = "0.3"
log = "0.4"
libboard_zynq = { git = "https://git.m-labs.hk/M-Labs/zc706.git" } libboard_zynq = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
libsupport_zynq = { git = "https://git.m-labs.hk/M-Labs/zc706.git" } libsupport_zynq = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
libcortex_a9 = { git = "https://git.m-labs.hk/M-Labs/zc706.git" } libcortex_a9 = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }

5
runtime/src/main.rs
View File

@ -2,6 +2,7 @@
#![no_main] #![no_main]
extern crate alloc; extern crate alloc;
extern crate log;
use core::{cmp, str}; use core::{cmp, str};
@ -9,7 +10,7 @@ use libboard_zynq::{
println, println,
self as zynq, clocks::Clocks, clocks::source::{ClockSource, ArmPll, IoPll}, self as zynq, clocks::Clocks, clocks::source::{ClockSource, ArmPll, IoPll},
}; };
use libsupport_zynq::ram; use libsupport_zynq::{logger, ram};
mod comms; mod comms;
mod pl; mod pl;
@ -33,6 +34,8 @@ fn identifier_read(buf: &mut [u8]) -> &str {
#[no_mangle] #[no_mangle]
pub fn main_core0() { pub fn main_core0() {
println!("ARTIQ runtime starting..."); println!("ARTIQ runtime starting...");
let _ = logger::init();
log::set_max_level(log::LevelFilter::Debug);
const CPU_FREQ: u32 = 800_000_000; const CPU_FREQ: u32 = 800_000_000;