From 8e3574080cfa23ac7ab4863c3ebcc3d90ce97e51 Mon Sep 17 00:00:00 2001
From: pca006132 <john.lck40@gmail.com>
Date: Tue, 14 Jul 2020 10:53:35 +0800
Subject: [PATCH] core1: added cache flush and barriers.

---
 src/runtime/src/kernel/core1.rs | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/src/runtime/src/kernel/core1.rs b/src/runtime/src/kernel/core1.rs
index cd633795..e1b78841 100644
--- a/src/runtime/src/kernel/core1.rs
+++ b/src/runtime/src/kernel/core1.rs
@@ -5,7 +5,12 @@ use alloc::borrow::ToOwned;
 use log::{debug, info, error};
 use cslice::CSlice;
 
-use libcortex_a9::{enable_fpu, cache::{dcci_slice, iciallu}, sync_channel};
+use libcortex_a9::{
+    enable_fpu,
+    cache::{dcci_slice, iciallu, bpiall},
+    asm::{dsb, isb},
+    sync_channel
+};
 use dyld::{self, Library};
 use crate::eh_artiq;
 use super::{
@@ -92,7 +97,11 @@ impl KernelImage {
         // Flush data cache entries for the image in DDR, including
         // Memory/Instruction Synchronization Barriers
         dcci_slice(self.library.image.data);
+        dsb();
         iciallu();
+        bpiall();
+        dsb();
+        isb();
 
         (mem::transmute::<u32, fn()>(self.__modinit__))();