forked from M-Labs/artiq-zynq
kasli_soc: enable clock buffer after system clock domain reset
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parent
f52c155006
commit
0d97eeb56a
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@ -84,6 +84,7 @@ fn init_rtio(timer: &mut GlobalTimer) {
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panic!("SYS CLK did not switch");
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panic!("SYS CLK did not switch");
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}
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}
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unsafe {
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unsafe {
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pl::csr::sys_crg::clock_switch_write(1); //re-enable clock input buffer after system clock domain reset
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pl::csr::rtio_core::reset_phy_write(1);
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pl::csr::rtio_core::reset_phy_write(1);
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}
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}
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info!("SYS PLL locked");
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info!("SYS PLL locked");
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@ -103,6 +104,7 @@ fn init_drtio(timer: &mut GlobalTimer) {
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panic!("SYS CLK did not switch");
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panic!("SYS CLK did not switch");
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}
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}
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unsafe {
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unsafe {
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pl::csr::drtio_transceiver::stable_clkin_write(1); //re-enable clock input buffer after system clock domain reset
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pl::csr::rtio_core::reset_phy_write(1);
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pl::csr::rtio_core::reset_phy_write(1);
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pl::csr::drtio_transceiver::txenable_write(0xffffffffu32 as _);
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pl::csr::drtio_transceiver::txenable_write(0xffffffffu32 as _);
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}
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}
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@ -642,6 +642,7 @@ pub extern "C" fn main_core0() -> i32 {
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}
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}
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unsafe {
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unsafe {
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csr::drtio_transceiver::stable_clkin_write(1); //re-enable clock input buffer after system clock domain reset
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csr::drtio_transceiver::txenable_write(0xffffffffu32 as _);
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csr::drtio_transceiver::txenable_write(0xffffffffu32 as _);
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}
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}
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