forked from M-Labs/zynq-rs
123 lines
3.8 KiB
Rust
123 lines
3.8 KiB
Rust
use volatile_register::{RO, WO, RW};
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use libregister::{register, register_at, register_bit, register_bits};
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#[repr(C)]
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pub struct RegisterBlock {
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pub config: Config,
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pub intr_status: IntrStatus,
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pub intr_en: IntrEn,
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pub intr_dis: IntrDis,
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pub intr_mask: RO<u32>,
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pub enable: Enable,
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pub delay: RW<u32>,
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pub txd0: WO<u32>,
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pub rx_data: RO<u32>,
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pub slave_idle_count: RW<u32>,
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pub tx_thres: RW<u32>,
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pub rx_thres: RW<u32>,
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pub gpio: QspiGpio,
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pub _unused1: RO<u32>,
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pub lpbk_dly_adj: RW<u32>,
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pub _unused2: [RO<u32>; 17],
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pub txd1: WO<u32>,
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pub txd2: WO<u32>,
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pub txd3: WO<u32>,
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pub _unused3: [RO<u32>; 5],
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pub lqspi_cfg: LqspiCfg,
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pub lqspi_sts: RW<u32>,
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pub _unused4: [RO<u32>; 21],
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pub mod_id: RW<u32>,
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}
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const BASE_ADDRESS: u32 = 0xE000D000;
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register_at!(RegisterBlock, 0xE000D000, qspi);
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register!(config, Config, RW, u32);
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register_bit!(config,
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/// Enables master mode
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mode_sel, 0);
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register_bit!(config,
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/// Clock polarity low/high
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clk_pol, 1);
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register_bit!(config,
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/// Clock phase
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clk_ph, 2);
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register_bits!(config,
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/// divider = 2 ** (1 + baud_rate_div)
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baud_rate_div, u8, 3, 5);
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register_bits!(config,
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/// Must be set to 0b11
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fifo_width, u8, 6, 7);
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register_bit!(config,
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/// Must be 0
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ref_clk, 8);
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register_bit!(config,
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/// Peripheral Chip Select Line
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pcs, 10);
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register_bit!(config,
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/// false: auto mode, true: manual CS mode
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manual_cs, 14);
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register_bit!(config,
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/// false: auto mode, true: enables manual start enable
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man_start_en, 15);
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register_bit!(config,
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/// false: auto mode, true: enables manual start command
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man_start_com, 16);
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register_bit!(config, holdb_dr, 19);
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register_bit!(config,
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/// false: little, true: endian
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endian, 26);
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register_bit!(config,
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/// false: legacy SPI mode, true: Flash memory interface mode
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leg_flsh, 31);
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register!(intr_status, IntrStatus, RW, u32);
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register_bit!(intr_status, rx_overflow, 0);
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register_bit!(intr_status,
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/// < tx_thres
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tx_fifo_not_full, 2);
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register_bit!(intr_status, tx_fifo_full, 3);
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register_bit!(intr_status,
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/// >= rx_thres
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rx_fifo_not_empty, 4);
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register_bit!(intr_status, rx_fifo_full, 5);
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register_bit!(intr_status, tx_fifo_underflow, 6);
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register!(intr_en, IntrEn, WO, u32);
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register_bit!(intr_en, rx_overflow, 0);
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register_bit!(intr_en, tx_fifo_not_full, 2);
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register_bit!(intr_en, tx_fifo_full, 3);
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register_bit!(intr_en, rx_fifo_not_empty, 4);
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register_bit!(intr_en, rx_fifo_full, 5);
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register_bit!(intr_en, tx_fifo_underflow, 6);
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register!(intr_dis, IntrDis, WO, u32);
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register_bit!(intr_dis, rx_overflow, 0);
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register_bit!(intr_dis, tx_fifo_not_full, 2);
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register_bit!(intr_dis, tx_fifo_full, 3);
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register_bit!(intr_dis, rx_fifo_not_empty, 4);
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register_bit!(intr_dis, rx_fifo_full, 5);
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register_bit!(intr_dis, tx_fifo_underflow, 6);
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register!(enable, Enable, RW, u32);
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register_bit!(enable, spi_en, 0);
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// named to avoid confusion with normal gpio
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register!(qspi_gpio, QspiGpio, RW, u32);
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register_bit!(qspi_gpio,
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/// Write protect pin (inverted)
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wp_n, 0);
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register!(lqspi_cfg, LqspiCfg, RW, u32);
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register_bits!(lqspi_cfg, inst_code, u8, 0, 7);
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register_bits!(lqspi_cfg, dummy_mask, u8, 8, 10);
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register_bits!(lqspi_cfg, mode_bits, u8, 16, 23);
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register_bit!(lqspi_cfg, mode_on, 24);
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register_bit!(lqspi_cfg, mode_en, 25);
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register_bit!(lqspi_cfg, u_page, 28);
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register_bit!(lqspi_cfg, sep_bus, 29);
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register_bit!(lqspi_cfg, two_mem, 30);
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register_bit!(lqspi_cfg, lq_mode, 31);
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