forked from M-Labs/zynq-rs
390 lines
13 KiB
Rust
390 lines
13 KiB
Rust
use libregister::{RegisterR, RegisterW, RegisterRW};
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use log::{debug, info, error};
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use crate::{print, println};
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use super::slcr::{self, DdriobVrefSel};
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use super::clocks::{Clocks, source::{DdrPll, ClockSource}};
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mod regs;
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#[cfg(feature = "target_zc706")]
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/// Micron MT41J256M8HX-15E: 667 MHz DDR3
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const DDR_FREQ: u32 = 666_666_666;
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#[cfg(feature = "target_cora_z7_10")]
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/// Micron MT41K256M16HA-125: 800 MHz DDR3L, max supported 533 MHz
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const DDR_FREQ: u32 = 525_000_000;
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#[cfg(feature = "target_redpitaya")]
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/// Alliance Memory AS4C256M16D3B: 800 MHz DDR3
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const DDR_FREQ: u32 = 800_000_000;
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/// MT41K256M16HA-125
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const DCI_FREQ: u32 = 10_000_000;
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pub struct DdrRam {
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regs: &'static mut regs::RegisterBlock,
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}
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impl DdrRam {
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pub fn ddrram() -> Self {
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let clocks = Self::clock_setup();
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Self::calibrate_iob_impedance(&clocks);
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Self::configure_iob();
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let regs = regs::RegisterBlock::ddrc();
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let mut ddr = DdrRam { regs };
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ddr.configure();
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ddr.reset_ddrc();
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ddr
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}
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/// Zynq-7000 AP SoC Technical Reference Manual:
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/// 10.6.1 DDR Clock Initialization
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fn clock_setup() -> Clocks {
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DdrPll::setup(2 * DDR_FREQ);
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let clocks = Clocks::get();
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let ddr3x_clk_divisor = 2;
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let ddr2x_clk_divisor = 3;
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debug!("DDR 3x/2x clocks: {}/{}", clocks.ddr / u32::from(ddr3x_clk_divisor), clocks.ddr / u32::from(ddr2x_clk_divisor));
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.ddr_clk_ctrl.write(
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slcr::DdrClkCtrl::zeroed()
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.ddr_2xclkact(true)
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.ddr_3xclkact(true)
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.ddr_2xclk_divisor(ddr2x_clk_divisor)
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.ddr_3xclk_divisor(ddr3x_clk_divisor)
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);
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});
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clocks
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}
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fn calculate_dci_divisors(clocks: &Clocks) -> (u8, u8) {
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let target = (DCI_FREQ - 1 + clocks.ddr) / DCI_FREQ;
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let mut best = None;
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let mut best_error = 0;
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for divisor0 in 1..63 {
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for divisor1 in 1..63 {
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let current = (divisor0 as u32) * (divisor1 as u32);
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let error = if current > target {
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current - target
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} else {
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target - current
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};
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if best.is_none() || best_error > error {
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best = Some((divisor0, divisor1));
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best_error = error;
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}
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}
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}
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best.unwrap()
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}
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/// Zynq-7000 AP SoC Technical Reference Manual:
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/// 10.6.2 DDR IOB Impedance Calibration
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fn calibrate_iob_impedance(clocks: &Clocks) {
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let (divisor0, divisor1) = Self::calculate_dci_divisors(clocks);
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debug!("DDR DCI clock: {} Hz (divisors={}*{})",
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clocks.ddr / u32::from(divisor0) / u32::from(divisor1),
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divisor0, divisor1);
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slcr::RegisterBlock::unlocked(|slcr| {
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// Step 1.
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slcr.dci_clk_ctrl.write(
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slcr::DciClkCtrl::zeroed()
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.clkact(true)
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.divisor0(divisor0)
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.divisor1(divisor1)
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);
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// Step 2.a.
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slcr.ddriob_dci_ctrl.modify(|_, w|
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w.reset(false)
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);
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slcr.ddriob_dci_ctrl.modify(|_, w|
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w.reset(true)
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);
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// Step 3.b. for DDR3/DDR3L
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slcr.ddriob_dci_ctrl.modify(|_, w|
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w.nref_opt1(0)
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.nref_opt2(0)
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.nref_opt4(1)
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.pref_opt1(0)
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.pref_opt2(0)
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);
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// Step 2.c.
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slcr.ddriob_dci_ctrl.modify(|_, w|
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w.update_control(false)
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);
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// Step 2.d.
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slcr.ddriob_dci_ctrl.modify(|_, w|
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w.enable(true)
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);
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// Step 2.e.
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while ! slcr.ddriob_dci_status.read().done() {}
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});
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}
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/// Zynq-7000 AP SoC Technical Reference Manual:
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/// 10.6.3 DDR IOB Configuration
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fn configure_iob() {
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slcr::RegisterBlock::unlocked(|slcr| {
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let addr_config = slcr::DdriobConfig::zeroed()
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.output_en(slcr::DdriobOutputEn::Obuf);
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slcr.ddriob_addr0.write(addr_config.clone());
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slcr.ddriob_addr1.write(addr_config);
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#[cfg(feature = "target_zc706")]
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let data0_config = slcr::DdriobConfig::zeroed()
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.inp_type(slcr::DdriobInputType::VrefDifferential)
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.term_en(true)
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.dci_type(slcr::DdriobDciType::Termination)
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.output_en(slcr::DdriobOutputEn::Obuf);
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#[cfg(feature = "target_zc706")]
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let data1_config = data0_config.clone();
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#[cfg(feature = "target_cora_z7_10")]
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let data0_config = slcr::DdriobConfig::zeroed()
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.inp_type(slcr::DdriobInputType::VrefDifferential)
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.term_en(true)
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.dci_type(slcr::DdriobDciType::Termination)
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.output_en(slcr::DdriobOutputEn::Obuf);
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#[cfg(feature = "target_cora_z7_10")]
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let data1_config = slcr::DdriobConfig::zeroed()
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.pullup_en(true);
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#[cfg(feature = "target_redpitaya")]
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let data0_config = slcr::DdriobConfig::zeroed()
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.inp_type(slcr::DdriobInputType::VrefDifferential)
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.term_en(true)
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.dci_type(slcr::DdriobDciType::Termination)
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.output_en(slcr::DdriobOutputEn::Obuf);
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#[cfg(feature = "target_redpitaya")]
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let data1_config = slcr::DdriobConfig::zeroed()
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.pullup_en(true);
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slcr.ddriob_data0.write(data0_config);
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slcr.ddriob_data1.write(data1_config);
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#[cfg(feature = "target_zc706")]
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let diff0_config = slcr::DdriobConfig::zeroed()
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.inp_type(slcr::DdriobInputType::Differential)
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.term_en(true)
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.dci_type(slcr::DdriobDciType::Termination)
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.output_en(slcr::DdriobOutputEn::Obuf);
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#[cfg(feature = "target_zc706")]
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let diff1_config = diff0_config.clone();
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#[cfg(feature = "target_cora_z7_10")]
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let diff0_config = slcr::DdriobConfig::zeroed()
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.inp_type(slcr::DdriobInputType::Differential)
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.term_en(true)
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.dci_type(slcr::DdriobDciType::Termination)
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.output_en(slcr::DdriobOutputEn::Obuf);
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#[cfg(feature = "target_cora_z7_10")]
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let diff1_config = slcr::DdriobConfig::zeroed()
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.pullup_en(true);
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#[cfg(feature = "target_redpitaya")]
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let diff0_config = slcr::DdriobConfig::zeroed()
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.inp_type(slcr::DdriobInputType::Differential)
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.term_en(true)
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.dci_type(slcr::DdriobDciType::Termination)
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.output_en(slcr::DdriobOutputEn::Obuf);
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#[cfg(feature = "target_redpitaya")]
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let diff1_config = slcr::DdriobConfig::zeroed()
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.pullup_en(true);
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slcr.ddriob_diff0.write(diff0_config);
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slcr.ddriob_diff1.write(diff1_config);
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slcr.ddriob_clock.write(
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slcr::DdriobConfig::zeroed()
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.output_en(slcr::DdriobOutputEn::Obuf)
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);
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unsafe {
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// Not documented in Technical Reference Manual
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slcr.ddriob_drive_slew_addr.write(0x0018C61C);
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slcr.ddriob_drive_slew_data.write(0x00F9861C);
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slcr.ddriob_drive_slew_diff.write(0x00F9861C);
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slcr.ddriob_drive_slew_clock.write(0x00F9861C);
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}
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// Enable external V[REF]
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#[cfg(feature = "target_cora_z7_10")]
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slcr.ddriob_ddr_ctrl.modify(|_, w| w
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.vref_int_en(false)
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.vref_ext_en_lower(true)
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.vref_ext_en_upper(false)
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);
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#[cfg(feature = "target_zc706")]
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slcr.ddriob_ddr_ctrl.modify(|_, w| w
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.vref_int_en(true)
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.vref_sel(DdriobVrefSel::Vref0_75V)
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.vref_ext_en_lower(false)
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.vref_ext_en_upper(false)
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);
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#[cfg(feature = "target_redpitaya")]
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slcr.ddriob_ddr_ctrl.modify(|_, w| w
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.vref_int_en(false)
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.vref_ext_en_lower(true)
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.vref_ext_en_upper(false)
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);
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});
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}
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fn configure(&mut self) {
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self.regs.dram_param0.write(
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regs::DramParam0::zeroed()
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.t_rc(0x1b)
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.t_rfc_min(0x56)
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.post_selfref_gap_x32(0x10)
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);
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self.regs.dram_param2.write(
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regs::DramParam2::zeroed()
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.write_latency(0x5)
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.rd2wr(0x7)
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.wr2rd(0xe)
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.t_xp(0x4)
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.pad_pd(0x0)
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.rd2pre(0x4)
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.t_rcd(0x7)
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);
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self.regs.dram_emr_mr.write(
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regs::DramEmrMr::zeroed()
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.mr(0x930)
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.emr(0x4)
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);
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self.regs.phy_cmd_timeout_rddata_cpt.modify(
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|_, w| w
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.rd_cmd_to_data(0x0)
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.wr_cmd_to_data(0x0)
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.we_to_re_delay(0x8)
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.rdc_fifo_rst_disable(false)
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.use_fixed_re(true)
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.rdc_fifo_rst_err_cnt_clr(false)
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.dis_phy_ctrl_rstn(false)
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.clk_stall_level(false)
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.gatelvl_num_of_dq0(0x7)
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.wrlvl_num_of_dq0(0x7)
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);
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self.regs.reg_2c.write(
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regs::Reg2C::zeroed()
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.wrlvl_max_x1024(0xfff)
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.rdlvl_max_x1024(0xfff)
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.twrlvl_max_error(false)
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.trdlvl_max_error(false)
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.dfi_wr_level_en(true)
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.dfi_rd_dqs_gate_level(true)
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.dfi_rd_data_eye_train(true)
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);
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self.regs.dfi_timing.write(
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regs::DfiTiming::zeroed()
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.rddata_en(0x6)
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.ctrlup_min(0x3)
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.ctrlup_max(0x40)
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);
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self.regs.phy_init_ratio3.write(
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regs::PhyInitRatio::zeroed()
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.wrlvl_init_ratio(0x21)
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.gatelvl_init_ratio(0xee)
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);
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self.regs.reg_65.write(
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regs::Reg65::zeroed()
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.wr_rl_delay(0x2)
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.rd_rl_delay(0x4)
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.dll_lock_diff(0xf)
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.use_wr_level(true)
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.use_rd_dqs_gate_level(true)
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.use_rd_data_eye_level(true)
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.dis_calib_rst(false)
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.ctrl_slave_delay(0x0)
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);
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}
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/// Reset DDR controller
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fn reset_ddrc(&mut self) {
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#[cfg(feature = "target_zc706")]
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unsafe {
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// row/column address bits
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self.regs.dram_addr_map_bank.write(0x00000777);
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self.regs.dram_addr_map_col.write(0xFFF00000);
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self.regs.dram_addr_map_row.write(0x0F666666);
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}
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#[cfg(feature = "target_zc706")]
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let width = regs::DataBusWidth::Width32bit;
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#[cfg(feature = "target_cora_z7_10")]
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let width = regs::DataBusWidth::Width16bit;
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#[cfg(feature = "target_redpitaya")]
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let width = regs::DataBusWidth::Width16bit;
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self.regs.ddrc_ctrl.modify(|_, w| w
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.soft_rstb(false)
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.powerdown_en(false)
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.data_bus_width(width)
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);
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self.regs.ddrc_ctrl.modify(|_, w| w
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.soft_rstb(true)
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.powerdown_en(false)
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.data_bus_width(width)
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);
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while self.status() == regs::ControllerStatus::Init {}
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}
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pub fn status(&self) -> regs::ControllerStatus {
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self.regs.mode_sts.read().operating_mode()
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}
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pub fn ptr<T>(&mut self) -> *mut T {
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0x0010_0000 as *mut _
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}
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/// actually there's 1 MB more but starting at 0x0000_0000
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/// overlaps with OCM.
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pub fn size(&self) -> usize {
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#[cfg(feature = "target_zc706")]
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let megabytes = 1023;
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#[cfg(feature = "target_cora_z7_10")]
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let megabytes = 511;
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#[cfg(feature = "target_redpitaya")]
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let megabytes = 511;
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megabytes * 1024 * 1024
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}
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pub fn memtest(&mut self) {
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let slice = unsafe {
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core::slice::from_raw_parts_mut(self.ptr(), self.size())
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};
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let patterns: &'static [u32] = &[0xffff_ffff, 0x5555_5555, 0xaaaa_aaaa, 0];
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let mut expected = None;
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for (i, pattern) in patterns.iter().enumerate() {
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info!("memtest phase {} (status: {:?})", i, self.status());
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for megabyte in 0..slice.len() / (1024 * 1024) {
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let start = megabyte * 1024 * 1024 / 4;
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let end = (megabyte + 1) * 1024 * 1024 / 4;
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for b in slice[start..end].iter_mut() {
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expected.map(|expected| {
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let read: u32 = *b;
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if read != expected {
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error!("{:08X}: expected {:08X}, read {:08X}", b as *mut _ as usize, expected, read);
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}
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});
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*b = *pattern;
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}
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print!("\r{} MB", megabyte);
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}
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println!(" Ok");
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expected = Some(*pattern);
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}
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}
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}
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