From aab82f684315cc5ef381c10b1c98cff381731d49 Mon Sep 17 00:00:00 2001
From: Astro <astro@spaceboyz.net>
Date: Tue, 10 Dec 2019 02:45:05 +0100
Subject: [PATCH] zynq::flash: enable big endian mode

---
 src/zynq/flash/bytes.rs | 12 ++++++------
 src/zynq/flash/mod.rs   |  1 +
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/src/zynq/flash/bytes.rs b/src/zynq/flash/bytes.rs
index 31b794f..5d35895 100644
--- a/src/zynq/flash/bytes.rs
+++ b/src/zynq/flash/bytes.rs
@@ -10,7 +10,7 @@ impl<I: Iterator<Item = u32>> BytesTransferExt for I {
     fn bytes_transfer(self) -> BytesTransfer<Self> {
         BytesTransfer {
             iter: self,
-            shift: 32,
+            shift: 0,
             word: 0,
         }
     }
@@ -26,15 +26,15 @@ impl<I: Iterator<Item = u32> + Sized> Iterator for BytesTransfer<I> {
     type Item = u8;
 
     fn next(&mut self) -> Option<u8> {
-        if self.shift < 24 {
-            self.shift += 8;
+        if self.shift > 0 {
+            self.shift -= 8;
             Some((self.word >> self.shift) as u8)
         } else {
-            self.shift = 0;
             self.iter.next()
-                .map(|word| {
+                .and_then(|word| {
+                    self.shift = 32;
                     self.word = word;
-                    word as u8
+                    self.next()
                 })
         }
     }
diff --git a/src/zynq/flash/mod.rs b/src/zynq/flash/mod.rs
index 8b294c2..e08e984 100644
--- a/src/zynq/flash/mod.rs
+++ b/src/zynq/flash/mod.rs
@@ -272,6 +272,7 @@ impl Flash<()> {
         self.regs.config.modify(|_, w| w
             .man_start_en(true)
             .manual_cs(true)
+            .endian(true)
         );
 
         self.regs.lqspi_cfg.write(regs::LqspiCfg::zeroed()