From 77c3998dbd1ecaedc4b48c403e26ac45c4af80f5 Mon Sep 17 00:00:00 2001 From: Astro Date: Mon, 22 Jun 2020 02:32:38 +0200 Subject: [PATCH] mmu: set L2-bufferable for DDR --- experiments/src/main.rs | 7 ++++++- libboard_zynq/Cargo.toml | 1 + libboard_zynq/src/eth/rx.rs | 8 ++++++++ libboard_zynq/src/eth/tx.rs | 9 ++++++++- libboard_zynq/src/lib.rs | 4 +++- libcortex_a9/src/mmu.rs | 2 +- libsupport_zynq/src/abort.rs | 3 +++ 7 files changed, 30 insertions(+), 4 deletions(-) diff --git a/experiments/src/main.rs b/experiments/src/main.rs index 4ce7db5..7e371bf 100644 --- a/experiments/src/main.rs +++ b/experiments/src/main.rs @@ -33,7 +33,7 @@ use libregister::RegisterR; use libsupport_zynq::{ boot, ram, }; -use log::info; +use log::{info, warn}; mod ps7_init; @@ -84,7 +84,9 @@ pub fn main_core0() { ); info!("Setup L2Cache"); setup_l2cache(); + info!("L2Cache done"); +if false { let sd = libboard_zynq::sdio::SDIO::sdio0(true); // only test SD card if it is inserted if sd.is_card_inserted() { @@ -117,6 +119,7 @@ pub fn main_core0() { println!(""); } let mut flash = flash.stop(); +} let timer = libboard_zynq::timer::GlobalTimer::start(); @@ -125,6 +128,7 @@ pub fn main_core0() { ddr.memtest(); ram::init_alloc_ddr(&mut ddr); +if false { #[cfg(dev)] for i in 0..=1 { let mut flash_io = flash.manual_mode(i); @@ -178,6 +182,7 @@ pub fn main_core0() { } }); core1.disable(); +} let eth = zynq::eth::Eth::default(HWADDR.clone()); println!("Eth on"); diff --git a/libboard_zynq/Cargo.toml b/libboard_zynq/Cargo.toml index cc3e522..3b36fcc 100644 --- a/libboard_zynq/Cargo.toml +++ b/libboard_zynq/Cargo.toml @@ -21,5 +21,6 @@ libcortex_a9 = { path = "../libcortex_a9" } [dependencies.smoltcp] version = "0.6" +# features = ["ethernet", "proto-ipv4", "socket-tcp", "log"] features = ["ethernet", "proto-ipv4", "socket-tcp"] default-features = false diff --git a/libboard_zynq/src/eth/rx.rs b/libboard_zynq/src/eth/rx.rs index 4efd0ec..aedbb14 100644 --- a/libboard_zynq/src/eth/rx.rs +++ b/libboard_zynq/src/eth/rx.rs @@ -2,6 +2,8 @@ use core::ops::Deref; use alloc::{vec, vec::Vec}; use libcortex_a9::{asm::*, cache::*, UncachedSlice}; use libregister::*; +use log::debug; +use crate::l2cache; use super::Buffer; #[derive(Debug)] @@ -83,6 +85,7 @@ impl DescList { ); // Flush buffer from cache, to be filled by the peripheral // before next read + l2cache().clean_invalidate_slice(&buffer[..]); dcci_slice(&buffer[..]); } @@ -105,6 +108,8 @@ impl DescList { let word1 = entry.word1.read(); let len = word1.frame_length_lsbs().into(); let buffer = &mut self.buffers[self.next][0..len]; + // l2cache().invalidate_slice(&mut buffer[..]); + // dcci_slice(&buffer[..]); self.next += 1; if self.next >= list_len { @@ -113,8 +118,10 @@ impl DescList { let pkt = PktRef { entry, buffer }; if word1.start_of_frame() && word1.end_of_frame() { + // debug!("pkt {}: {:08X}..{:08X}", len, &pkt.buffer[0] as *const _ as usize, &pkt.buffer[pkt.len()-1] as *const _ as usize); Ok(Some(pkt)) } else { + debug!("pkt trunc"); Err(Error::Truncated) } } else { @@ -133,6 +140,7 @@ impl<'a> Drop for PktRef<'a> { fn drop(&mut self) { // Flush buffer from cache, to be filled by the peripheral // before next read + l2cache().invalidate_slice(self.buffer); dcci_slice(self.buffer); self.entry.word0.modify(|_, w| w.used(false)); diff --git a/libboard_zynq/src/eth/tx.rs b/libboard_zynq/src/eth/tx.rs index aa3c696..a25a4a3 100644 --- a/libboard_zynq/src/eth/tx.rs +++ b/libboard_zynq/src/eth/tx.rs @@ -2,7 +2,8 @@ use core::ops::{Deref, DerefMut}; use alloc::{vec, vec::Vec}; use libcortex_a9::{cache::dcc_slice, UncachedSlice}; use libregister::*; -use log::warn; +use log::{debug, warn}; +use crate::l2cache; use super::{Buffer, regs}; /// Descriptor entry @@ -91,8 +92,10 @@ impl DescList { } pub fn send<'s: 'p, 'p>(&'s mut self, regs: &'s mut regs::RegisterBlock, length: usize) -> Option> { + // debug!("send {}", length); let list_len = self.list.len(); let entry = &mut self.list[self.next]; + // dmb(); if entry.word1.read().used() { let buffer = &mut self.buffers[self.next][0..length]; entry.word1.write(DescWord1::zeroed() @@ -128,8 +131,12 @@ impl<'a> Drop for PktRef<'a> { fn drop(&mut self) { // Write back all dirty cachelines of this buffer dcc_slice(self.buffer); + l2cache().clean_slice(self.buffer); self.entry.word1.modify(|_, w| w.used(false)); + // dcci(self.entry); + // l2cache().clean_invalidate(self.entry); + // dsb(); if ! self.regs.tx_status.read().tx_go() { // Start TX if not already running self.regs.net_ctrl.modify(|_, w| w.start_tx(true)); diff --git a/libboard_zynq/src/lib.rs b/libboard_zynq/src/lib.rs index c3494a9..dc74c6e 100644 --- a/libboard_zynq/src/lib.rs +++ b/libboard_zynq/src/lib.rs @@ -34,8 +34,10 @@ pub fn setup_l2cache() { assert_eq!(&slcr.unnamed1 as *const _ as u32, 0xF8000A1C); unsafe { slcr.unnamed1.write(0x020202); } }); - + let mut l2 = l2cache(); + use log::info; + info!("l2 aux={:08X}", l2.regs.aux_control.read()); // TODO: set prefetch // Configure ZYNQ-specific latency diff --git a/libcortex_a9/src/mmu.rs b/libcortex_a9/src/mmu.rs index 151386b..ad52b8a 100644 --- a/libcortex_a9/src/mmu.rs +++ b/libcortex_a9/src/mmu.rs @@ -158,7 +158,7 @@ impl L1Table { global: true, shareable: true, access: AccessPermissions::FullAccess, - tex: 0b101, + tex: 0b111, domain: 0b1111, exec: true, cacheable: true, diff --git a/libsupport_zynq/src/abort.rs b/libsupport_zynq/src/abort.rs index 3d6592f..ab85331 100644 --- a/libsupport_zynq/src/abort.rs +++ b/libsupport_zynq/src/abort.rs @@ -1,3 +1,5 @@ +use libregister::RegisterR; +use libcortex_a9::regs::DFSR; use libboard_zynq::{println, slcr, stdio}; #[no_mangle] @@ -15,6 +17,7 @@ pub unsafe extern "C" fn DataAbort() { stdio::drop_uart(); println!("DataAbort"); + println!("DFSR: {:03X}", DFSR.read()); slcr::RegisterBlock::unlocked(|slcr| slcr.soft_reset()); loop {}