From 58cf9833cc35cd93d585e14737b943a5f6666d60 Mon Sep 17 00:00:00 2001 From: Astro Date: Mon, 21 Oct 2019 22:10:51 +0200 Subject: [PATCH] slcr: implement PllCfg and DdrClkCtrl --- src/slcr.rs | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/src/slcr.rs b/src/slcr.rs index df714ec..b12dacf 100644 --- a/src/slcr.rs +++ b/src/slcr.rs @@ -30,12 +30,12 @@ pub struct RegisterBlock { pub ddr_pll_ctrl: PllCtrl, pub io_pll_ctrl: PllCtrl, pub pll_status: RO, - pub arm_pll_cfg: RW, - pub ddr_pll_cfg: RW, - pub io_pll_cfg: RW, + pub arm_pll_cfg: PllCfg, + pub ddr_pll_cfg: PllCfg, + pub io_pll_cfg: PllCfg, reserved1: [u32; 1], pub arm_clk_ctrl: ArmClkCtrl, - pub ddr_clk_ctrl: RW, + pub ddr_clk_ctrl: DdrClkCtrl, pub dci_clk_ctrl: RW, pub aper_clk_ctrl: AperClkCtrl, pub usb0_clk_ctrl: RW, @@ -253,6 +253,11 @@ register_bit!(pll_ctrl, pll_bypass_qual, 3); register_bit!(pll_ctrl, pll_pwrdwn, 1); register_bit!(pll_ctrl, pll_reset, 0); +register!(pll_cfg, PllCfg, RW, u32); +register_bits!(pll_cfg, pll_res, u8, 4, 7); +register_bits!(pll_cfg, pll_cp, u8, 8, 11); +register_bits!(pll_cfg, lock_cnt, u16, 12, 21); + register!(arm_clk_ctrl, ArmClkCtrl, RW, u32); register_bit!(arm_clk_ctrl, /// Clock active @@ -264,6 +269,12 @@ register_bit!(arm_clk_ctrl, cpu_6or4xclkact, 24); register_bits!(arm_clk_ctrl, divisor, u8, 8, 13); register_bits_typed!(arm_clk_ctrl, srcsel, u8, ArmPllSource, 8, 13); +register!(ddr_clk_ctrl, DdrClkCtrl, RW, u32); +register_bit!(ddr_clk_ctrl, ddr_3xclkact, 0); +register_bit!(ddr_clk_ctrl, ddr_2xclkact, 1); +register_bits!(ddr_clk_ctrl, ddr_3xclk_divisor, u8, 20, 25); +register_bits!(ddr_clk_ctrl, ddr_2xclk_divisor, u8, 26, 31); + register!(clk_621_true, Clk621True, RW, u32); register_bit!(clk_621_true, clk_621_true, 0);