From 27114aec621a301f27839ca3de93c00a915588d6 Mon Sep 17 00:00:00 2001 From: Astro Date: Sun, 27 Oct 2019 20:30:38 +0100 Subject: [PATCH] zynq::ddr: fix PLL_FDIV_LOCK_PARAM usage this seems to make DDR RAM work. --- src/zynq/clocks.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/zynq/clocks.rs b/src/zynq/clocks.rs index 0d33cb6..83c5c34 100644 --- a/src/zynq/clocks.rs +++ b/src/zynq/clocks.rs @@ -102,7 +102,7 @@ impl CpuClocks { ); let (pll_res, pll_cp, lock_cnt) = PLL_FDIV_LOCK_PARAM.iter() .filter(|(fdiv_max, _)| fdiv <= *fdiv_max) - .last() + .nth(0) .expect("PLL_FDIV_LOCK_PARAM") .1.clone(); regs.ddr_pll_cfg.write(