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Author SHA1 Message Date
Astro 41d8af754a runtime: retain BufferLogger within LOGGER 2020-07-13 00:52:06 +02:00
pca006132 9611be657c Runtime: porting liblogger_artiq 2020-07-09 17:32:30 +08:00
75 changed files with 23773 additions and 3378 deletions
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165
LICENSE
View File

@ -1,165 +0,0 @@
GNU LESSER GENERAL PUBLIC LICENSE
Version 3, 29 June 2007
Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
This version of the GNU Lesser General Public License incorporates
the terms and conditions of version 3 of the GNU General Public
License, supplemented by the additional permissions listed below.
0. Additional Definitions.
As used herein, "this License" refers to version 3 of the GNU Lesser
General Public License, and the "GNU GPL" refers to version 3 of the GNU
General Public License.
"The Library" refers to a covered work governed by this License,
other than an Application or a Combined Work as defined below.
An "Application" is any work that makes use of an interface provided
by the Library, but which is not otherwise based on the Library.
Defining a subclass of a class defined by the Library is deemed a mode
of using an interface provided by the Library.
A "Combined Work" is a work produced by combining or linking an
Application with the Library. The particular version of the Library
with which the Combined Work was made is also called the "Linked
Version".
The "Minimal Corresponding Source" for a Combined Work means the
Corresponding Source for the Combined Work, excluding any source code
for portions of the Combined Work that, considered in isolation, are
based on the Application, and not on the Linked Version.
The "Corresponding Application Code" for a Combined Work means the
object code and/or source code for the Application, including any data
and utility programs needed for reproducing the Combined Work from the
Application, but excluding the System Libraries of the Combined Work.
1. Exception to Section 3 of the GNU GPL.
You may convey a covered work under sections 3 and 4 of this License
without being bound by section 3 of the GNU GPL.
2. Conveying Modified Versions.
If you modify a copy of the Library, and, in your modifications, a
facility refers to a function or data to be supplied by an Application
that uses the facility (other than as an argument passed when the
facility is invoked), then you may convey a copy of the modified
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ensure that, in the event an Application does not supply the
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whatever part of its purpose remains meaningful, or
b) under the GNU GPL, with none of the additional permissions of
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3. Object Code Incorporating Material from Library Header Files.
The object code form of an Application may incorporate material from
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d) Do one of the following:
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the Linked Version to produce a modified Combined Work, in the
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Corresponding Source.
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Library side by side in a single library together with other library
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b) Give prominent notice with the combined library that part of it
is a work based on the Library, and explaining where to find the
accompanying uncombined form of the same work.
6. Revised Versions of the GNU Lesser General Public License.
The Free Software Foundation may publish revised and/or new versions
of the GNU Lesser General Public License from time to time. Such new
versions will be similar in spirit to the present version, but may
differ in detail to address new problems or concerns.
Each version is given a distinguishing version number. If the
Library as you received it specifies that a certain numbered version
of the GNU Lesser General Public License "or any later version"
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Library.

65
README.md
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@ -1,34 +1,3 @@
ARTIQ on Zynq
=============
How to use
----------
1. Install ARTIQ-6 or newer.
2. Select the latest successful build on Hydra: https://nixbld.m-labs.hk/jobset/artiq/zynq
3. Search for the job named ``<board>-<variant>-sd`` (for example: ``zc706-nist_clock-sd`` or ``zc706-nist_qc2-sd``).
4. Download the ``boot.bin`` "binary distribution" and place it at the root of a FAT-formatted SD card.
5. Optionally, create a ``config.txt`` configuration file at the root of the SD card containing ``key=value`` pairs on each line. Use the ``ip``, ``ip6`` and ``mac`` keys to respectively set the IPv4, IPv6 and MAC address of the board. Configuring an IPv6 address is entirely optional. If these keys are not found, the firmware will use default values that may or may not be compatible with your network.
6. Insert the SD card into the board and set up the board to boot from the SD card. For the ZC706, this is achieved by placing the large DIP switch SW11 in the 00110 position.
7. Power up the board. After the firmware starts successfully, it should respond to ping at its IP addresses, and boot messages can be observed from its UART at 115200bps.
8. Create and use an ARTIQ device database as usual, but set ``"target": "cortexa9"`` in the arguments of the core device.
Configuration
-------------
Configuring the device is done using the ``config.txt`` text file at the root of the SD card, plus the contents of the ``config`` folder. When searching for a configuration key, the firmware first looks for a file named ``/config/[key].bin`` and, if it exists, returns the contents of that file. If not, it looks into ``/config.txt``, which contains a list of ``key=value`` pairs, one per line. The ``config`` folder allows configuration values that consist in binary data, such as the startup kernel.
The following configuration keys are available:
- ``mac``: Ethernet MAC address.
- ``ip``: IPv4 address.
- ``ip6``: IPv6 address.
- ``startup``: startup kernel in ELF format (as produced by ``artiq_compile``).
- ``rtioclk``: source of RTIO clock; valid values are ``external`` and ``internal``.
Development instructions
------------------------
Configure Nix channels:
```shell
@ -36,46 +5,22 @@ nix-channel --add https://nixbld.m-labs.hk/channel/custom/artiq/fast-beta/artiq-
nix-channel --update
```
Note: if you are using Nix channels the first time, you need to be aware of this bug: https://github.com/NixOS/nix/issues/3831
Pure build with Nix and execution on a remote JTAG server:
Pure build with Nix:
```shell
nix-build -A zc706-simple-jtag # or zc706-nist_qc2-jtag or zc706-nist_clock-jtag
./remote_run.sh
```
Impure incremental build and execution on a remote JTAG server:
Impure incremental build:
```shell
nix-shell
cd src
gateware/zc706.py -g ../build/gateware # build gateware
make # build firmware
./zc706.py -g ../build/gateware # build gateware
make # build firmware
cd ..
./remote_run.sh -i
```
Notes:
- This is known to work with Nixpkgs 20.03 and the ``nixbld.m-labs.hk`` binary substituter can also be used here (see the ARTIQ manual for the public key and instructions).
- The impure build process is also compatible with non-Nix systems.
- If the board is connected to the local machine, use the ``local_run.sh`` script.
License
-------
Copyright (C) 2019-2020 M-Labs Limited.
ARTIQ is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
ARTIQ is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public License
along with ARTIQ. If not, see <http://www.gnu.org/licenses/>.
The impure build process can also be used on non-Nix systems.

23
cargo-xbuild.nix
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@ -1,23 +0,0 @@
{ pkgs }:
pkgs.rustPlatform.buildRustPackage rec {
pname = "cargo-xbuild";
version = "0.5.21";
src = pkgs.fetchFromGitHub {
owner = "rust-osdev";
repo = pname;
rev = "v${version}";
sha256 = "08mpnj3l6bcm1jg22lw1gcs0lkm4320fwl4p5y1s44w64963kzf7";
};
patches = [ ./cargo-xbuild.patch ];
cargoSha256 = "1pj4x8y5vfpnn8vhxqqm3vicn29870r3jh0b17q3riq4vz1a2afp";
meta = with pkgs.stdenv.lib; {
description = "Automatically cross-compiles the sysroot crates core, compiler_builtins, and alloc";
homepage = "https://github.com/rust-osdev/cargo-xbuild";
license = with licenses; [ mit asl20 ];
maintainers = with maintainers; [ johntitor xrelkd ];
};
}

13
cargo-xbuild.patch
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@ -1,13 +0,0 @@
diff --git a/src/sysroot.rs b/src/sysroot.rs
index 1f3c8d1..e5615ee 100644
--- a/src/sysroot.rs
+++ b/src/sysroot.rs
@@ -163,7 +163,7 @@ version = "0.0.0"
edition = "2018"
[dependencies.compiler_builtins]
-version = "0.1.0"
+git = "https://git.m-labs.hk/M-Labs/compiler-builtins-zynq.git"
"#;
let mut stoml = TOML.to_owned();

15068
channel-rust-nightly.toml Normal file
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File diff suppressed because it is too large Load Diff

60
default.nix
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@ -1,19 +1,20 @@
{
mozillaOverlay ? import (builtins.fetchTarball https://github.com/mozilla/nixpkgs-mozilla/archive/master.tar.gz),
}:
let
zynq-rs = (import ./zynq-rs.nix);
pkgs = import <nixpkgs> { overlays = [ (import "${zynq-rs}/nix/mozilla-overlay.nix") ]; };
rustPlatform = (import "${zynq-rs}/nix/rust-platform.nix" { inherit pkgs; });
zc706-szl = (import zynq-rs).zc706-szl;
zc706-fsbl = import "${zynq-rs}/nix/fsbl.nix" { inherit pkgs; };
mkbootimage = import "${zynq-rs}/nix/mkbootimage.nix" { inherit pkgs; };
pkgs = import <nixpkgs> { overlays = [ mozillaOverlay ]; };
rustPlatform = (import ./rustPlatform.nix { inherit pkgs; });
artiqpkgs = import <artiq-fast/default.nix> { inherit pkgs; };
vivado = import <artiq-fast/vivado.nix> { inherit pkgs; };
mkbootimage = (import ./mkbootimage.nix { inherit pkgs; });
build-zc706 = { variant }: let
firmware = rustPlatform.buildRustPackage rec {
name = "zc706-${variant}-firmware";
version = "0.1.0";
src = ./src;
cargoSha256 = "10hap25cy2qgwr7b86jid73i6fp480iym29r3r97jindfxk0svi0";
cargoSha256 = "0xminds5fyp7c9vsx651zv3yzyhxnl9a02rhjl2wfxf8m679r45l";
nativeBuildInputs = [
pkgs.gnumake
@ -30,10 +31,10 @@ let
installPhase = ''
mkdir -p $out $out/nix-support
cp ../build/runtime.bin $out/runtime.bin
cp ../build/firmware/armv7-none-eabihf/release/runtime $out/runtime.elf
echo file binary-dist $out/runtime.bin >> $out/nix-support/hydra-build-products
cp ../build/firmware/armv7-none-eabihf/release/szl $out/szl.elf
echo file binary-dist $out/runtime.elf >> $out/nix-support/hydra-build-products
echo file binary-dist $out/szl.elf >> $out/nix-support/hydra-build-products
'';
doCheck = false;
@ -47,18 +48,16 @@ let
];
}
''
python ${./src/gateware}/zc706.py -g build -V ${variant}
python ${./src/zc706.py} -g build -V ${variant}
mkdir -p $out $out/nix-support
cp build/top.bit $out
echo file binary-dist $out/top.bit >> $out/nix-support/hydra-build-products
'';
# SZL startup
jtag = pkgs.runCommand "zc706-${variant}-jtag" {}
''
mkdir $out
ln -s ${zc706-szl}/szl.elf $out
ln -s ${firmware}/runtime.bin $out
ln -s ${firmware}/szl.elf $out
ln -s ${gateware}/top.bit $out
'';
sd = pkgs.runCommand "zc706-${variant}-sd"
@ -70,39 +69,13 @@ let
# can't write software (mkbootimage will segfault).
bifdir=`mktemp -d`
cd $bifdir
ln -s ${zc706-szl}/szl.elf szl.elf
ln -s ${firmware}/runtime.elf runtime.elf
ln -s ${firmware}/szl.elf szl.elf
ln -s ${gateware}/top.bit top.bit
cat > boot.bif << EOF
the_ROM_image:
{
[bootloader]szl.elf
top.bit
runtime.elf
}
EOF
mkdir $out $out/nix-support
mkbootimage boot.bif $out/boot.bin
echo file binary-dist $out/boot.bin >> $out/nix-support/hydra-build-products
'';
# FSBL startup
fsbl-sd = pkgs.runCommand "zc706-${variant}-fsbl-sd"
{
buildInputs = [ mkbootimage ];
}
''
bifdir=`mktemp -d`
cd $bifdir
ln -s ${zc706-fsbl}/fsbl.elf fsbl.elf
ln -s ${gateware}/top.bit top.bit
ln -s ${firmware}/runtime.elf runtime.elf
cat > boot.bif << EOF
the_ROM_image:
{
[bootloader]fsbl.elf
top.bit
runtime.elf
}
EOF
mkdir $out $out/nix-support
@ -114,15 +87,10 @@ let
"zc706-${variant}-gateware" = gateware;
"zc706-${variant}-jtag" = jtag;
"zc706-${variant}-sd" = sd;
"zc706-${variant}-fsbl-sd" = fsbl-sd;
};
in
(
(build-zc706 { variant = "simple"; }) //
(build-zc706 { variant = "nist_clock"; }) //
(build-zc706 { variant = "nist_qc2"; }) //
(build-zc706 { variant = "acpki_simple"; }) //
(build-zc706 { variant = "acpki_nist_clock"; }) //
(build-zc706 { variant = "acpki_nist_qc2"; }) //
{ inherit zynq-rs; }
(build-zc706 { variant = "nist_qc2"; })
)

49
examples/device_db.py
View File

@ -1,5 +1,3 @@
# For NIST_QC2
device_db = {
"core": {
"type": "local",
@ -12,24 +10,7 @@ device_db = {
"target": "cortexa9"
}
},
"core_cache": {
"type": "local",
"module": "artiq.coredevice.cache",
"class": "CoreCache"
},
"core_dma": {
"type": "local",
"module": "artiq.coredevice.dma",
"class": "CoreDMA"
},
"i2c_switch": {
"type": "local",
"module": "artiq.coredevice.i2c",
"class": "PCA9548"
},
# led? are common to all variants
"led0": {
"type": "local",
"module": "artiq.coredevice.ttl",
@ -55,33 +36,3 @@ device_db = {
"arguments": {"channel": 3}
},
}
# TTLs on QC2 backplane
for i in range(40):
device_db["ttl" + str(i)] = {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLInOut",
"arguments": {"channel": 4+i}
}
device_db["ad9914dds0"] = {
"type": "local",
"module": "artiq.coredevice.ad9914",
"class": "AD9914",
"arguments": {"sysclk": 3e9, "bus_channel": 50, "channel": 0},
}
device_db["ad9914dds1"] = {
"type": "local",
"module": "artiq.coredevice.ad9914",
"class": "AD9914",
"arguments": {"sysclk": 3e9, "bus_channel": 50, "channel": 1},
}
# for ARTIQ test suite
device_db.update(
loop_out="ttl0",
loop_in="ttl1",
ttl_out="ttl2",
ttl_out_serdes="ttl2",
)

26
examples/dma.py
View File

@ -1,26 +0,0 @@
from artiq.experiment import *
class DMAPulses(EnvExperiment):
def build(self):
self.setattr_device("core")
self.setattr_device("core_dma")
self.setattr_device("led0")
@kernel
def record(self):
with self.core_dma.record("pulse"):
delay(200*ms)
# all RTIO operations now go to the "pulse"
# DMA buffer, instead of being executed immediately.
self.led0.pulse(500*ms)
@kernel
def run(self):
self.core.reset()
self.record()
# prefetch the address of the DMA buffer
# for faster playback trigger
pulse_handle = self.core_dma.get_handle("pulse")
self.core.break_realtime()
self.core_dma.playback_handle(pulse_handle)

28
local_run.sh
View File

@ -2,20 +2,10 @@
set -e
if [ -z "$OPENOCD_ZYNQ" ]; then
echo "OPENOCD_ZYNQ environment variable must be set"
exit 1
fi
if [ -z "$SZL" ]; then
echo "SZL environment variable must be set"
exit 1
fi
impure=0
load_bitstream=1
board_host="192.168.1.52"
while getopts "ilb:" opt; do
while getopts "h:il" opt; do
case "$opt" in
\?) exit 1
;;
@ -23,26 +13,20 @@ while getopts "ilb:" opt; do
;;
l) load_bitstream=0
;;
b) board_host=$OPTARG
;;
esac
done
load_bitstream_cmd=""
build_dir=`pwd`/build
result_dir=`pwd`/result
cd $OPENOCD_ZYNQ
openocd -f zc706.cfg -c "load_image $SZL; resume 0; exit"
sleep 5
cd openocd
if [ $impure -eq 1 ]; then
if [ $load_bitstream -eq 1 ]; then
load_bitstream_cmd="-g $build_dir/gateware/top.bit"
load_bitstream_cmd="pld load 0 ../build/gateware/top.bit;"
fi
artiq_netboot $load_bitstream_cmd -f $build_dir/runtime.bin -b $board_host
openocd -f zc706.cfg -c "$load_bitstream_cmd load_image ../build/firmware/armv7-none-eabihf/release/szl; resume 0; exit"
else
if [ $load_bitstream -eq 1 ]; then
load_bitstream_cmd="-g $result_dir/top.bit"
load_bitstream_cmd="pld load 0 ../result/top.bit;"
fi
artiq_netboot $load_bitstream_cmd -f $result_dir/runtime.bin -b $board_host
openocd -f zc706.cfg -c "$load_bitstream_cmd load_image ../result/szl.elf; resume 0; exit"
fi

24
mkbootimage.nix Normal file
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@ -0,0 +1,24 @@
{ pkgs }:
pkgs.stdenv.mkDerivation {
pname = "mkbootimage";
version = "2.2";
src = pkgs.fetchFromGitHub {
owner = "antmicro";
repo = "zynq-mkbootimage";
rev = "4ee42d782a9ba65725ed165a4916853224a8edf7";
sha256 = "1k1mbsngqadqihzjgvwvsrkvryxy5ladpxd9yh9iqn2s7fxqwqa9";
};
propagatedBuildInputs = [ pkgs.libelf pkgs.pcre ];
patchPhase =
''
substituteInPlace Makefile --replace "git rev-parse --short HEAD" "echo nix"
'';
installPhase =
''
mkdir -p $out/bin
cp mkbootimage $out/bin
'';
}

18
openocd/digilent_jtag_smt2_nc.cfg Normal file
View File

@ -0,0 +1,18 @@
#
# Digilent JTAG-SMT2-NC
#
# http://store.digilentinc.com/jtag-smt2-nc-surface-mount-programming-module/
# https://reference.digilentinc.com/_media/jtag_smt2nc/jtag-smt2-nc_rm.pdf
#
# Based on reference sheet (above) and Xilinx KCU105 schematics
# https://www.xilinx.com/products/boards-and-kits/kcu105.html#documentation
#
# Note that the digilent_jtag_smt2 layout does not work and hangs while
# the ftdi_device_desc from digilent_hs2 is wrong.
interface ftdi
ftdi_device_desc "Digilent USB Device"
ftdi_vid_pid 0x0403 0x6014
ftdi_channel 0
ftdi_layout_init 0x00e8 0x60eb
ftdi_layout_signal nSRST -data 0x2000

40
openocd/zc706.cfg Normal file
View File

@ -0,0 +1,40 @@
source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg]
adapter_khz 1000
set PL_TAPID 0x23731093
set SMP 1
source ./zynq-7000.cfg
reset_config srst_only srst_open_drain
adapter_nsrst_assert_width 250
adapter_nsrst_delay 400
set XC7_JSHUTDOWN 0x0d
set XC7_JPROGRAM 0x0b
set XC7_JSTART 0x0c
set XC7_BYPASS 0x3f
proc xc7_program {tap} {
global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS
irscan $tap $XC7_JSHUTDOWN
irscan $tap $XC7_JPROGRAM
runtest 60000
#JSTART prevents this from working...
#irscan $tap $XC7_JSTART
runtest 2000
irscan $tap $XC7_BYPASS
runtest 2000
}
pld device virtex2 zynq.tap 1
init
xc7_program zynq.tap
reset halt
# Disable MMU
targets $_TARGETNAME_1
arm mcr 15 0 1 0 0 [expr [arm mrc 15 0 1 0 0] & ~0xd]
targets $_TARGETNAME_0
arm mcr 15 0 1 0 0 [expr [arm mrc 15 0 1 0 0] & ~0xd]

95
openocd/zynq-7000.cfg Normal file
View File

@ -0,0 +1,95 @@
#
# Xilinx Zynq 7000 SoC
#
# Chris Johns <chrisj@rtems.org>
#
# Setup
# -----
#
# Create a user configuration following the "Configuration Basics" in the user
# documentation. In the file have:
#
# source [find interface/ftdi/flyswatter2.cfg]
# source [find board/zynq-zc706-eval.cfg]
# adapter_khz 2000
# init
#
if { [info exists CHIPNAME] } {
global _CHIPNAME
set _CHIPNAME $CHIPNAME
} else {
global _CHIPNAME
set _CHIPNAME zynq
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
# this defaults to a bigendian
set _ENDIAN little
}
if { [info exists SMP] } {
global _SMP
set _SMP 1
} else {
global _SMP
set _SMP 0
}
#
# PL Tap.
#
# See ug585 ZYNQ-7000 TRM PSS_IDCODE for how this number is constructed.
# 0x03731093 - ZC706 Eval board 1.1
# 0x23731093 - ??
# 0x23727093 - Zedboard Rev. C and D
#
# Set in your configuration file or board specific file.
#
if { [info exists PL_TAPID] } {
set _PL_TAPID $PL_TAPID
} else {
set _PL_TAPID 0x03731093
}
jtag newtap $_CHIPNAME tap -irlen 6 -ircapture 0x001 -irmask 0x003 \
-expected-id $_PL_TAPID
#
# CoreSight Debug Access Port
#
if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x4ba00477
}
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x03 \
-expected-id $_DAP_TAPID
#
# GDB target: Cortex-A9, using DAP, configuring only one core
# Base addresses of cores:
# core 0 - 0xF8890000
# core 1 - 0xF8892000
#
# Read from the ROM table with the patch to read the nested table.
#
set _TARGETNAME_0 $_CHIPNAME.cpu.0
set _TARGETNAME_1 $_CHIPNAME.cpu.1
target create $_TARGETNAME_0 cortex_a -coreid 0 \
-endian $_ENDIAN \
-chain-position $_CHIPNAME.dap \
-dbgbase 0x80090000
if { $_SMP } {
echo "Zynq CPU1."
target create $_TARGETNAME_1 cortex_a -coreid 1 \
-endian $_ENDIAN \
-chain-position $_CHIPNAME.dap \
-dbgbase 0x80092000
target smp $_TARGETNAME_0 $_TARGETNAME_1
}

30
remote_run.sh
View File

@ -2,22 +2,12 @@
set -e
if [ -z "$OPENOCD_ZYNQ" ]; then
echo "OPENOCD_ZYNQ environment variable must be set"
exit 1
fi
if [ -z "$SZL" ]; then
echo "SZL environment variable must be set"
exit 1
fi
target_host="rpi-4.m-labs.hk"
impure=0
pure_dir="result"
impure_dir="build"
sshopts=""
load_bitstream=1
board_host="192.168.1.52"
while getopts "h:id:o:l" opt; do
case "$opt" in
@ -34,31 +24,29 @@ while getopts "h:id:o:l" opt; do
;;
l) load_bitstream=0
;;
b) board_host=$OPTARG
;;
esac
done
target_folder="/tmp/zynq-$USER"
load_bitstream_cmd=""
if [ $load_bitstream -eq 1 ]; then
load_bitstream_cmd="pld load 0 top.bit;"
fi
echo "Creating $target_folder..."
ssh $sshopts $target_host "mkdir -p $target_folder"
echo "Copying files..."
rsync -e "ssh $sshopts" -Lc $OPENOCD_ZYNQ/* $target_host:$target_folder
rsync -e "ssh $sshopts" -Lc $SZL $target_host:$target_folder
rsync -e "ssh $sshopts" openocd/* $target_host:$target_folder
if [ $impure -eq 1 ]; then
rsync -e "ssh $sshopts" $impure_dir/firmware/armv7-none-eabihf/release/szl $target_host:$target_folder/szl.elf
if [ $load_bitstream -eq 1 ]; then
load_bitstream_cmd="-g build/gateware/top.bit"
rsync -e "ssh $sshopts" $impure_dir/gateware/top.bit $target_host:$target_folder
fi
firmware="build/runtime.bin"
else
rsync -e "ssh $sshopts" -Lc $pure_dir/szl.elf $target_host:$target_folder
if [ $load_bitstream -eq 1 ]; then
load_bitstream_cmd="-g $pure_dir/top.bit"
rsync -e "ssh $sshopts" -Lc $pure_dir/top.bit $target_host:$target_folder
fi
firmware="$pure_dir/runtime.bin"
fi
echo "Programming board..."
ssh $sshopts $target_host "cd $target_folder; openocd -f zc706.cfg -c'load_image szl.elf; resume 0; exit'"
sleep 5
artiq_netboot $load_bitstream_cmd -f $firmware -b $board_host
ssh $sshopts $target_host "cd $target_folder; openocd -f zc706.cfg -c'$load_bitstream_cmd load_image szl.elf; resume 0; exit'"

24
rustPlatform.nix Normal file
View File

@ -0,0 +1,24 @@
{ pkgs }:
let
rustcSrc = pkgs.fetchgit {
url = "https://github.com/rust-lang/rust.git";
# master of 2020-04-10
rev = "94d346360da50f159e0dc777dc9bc3c5b6b51a00";
sha256 = "1hcqdz4w2vqb12rrqqcjbfs5s0w4qwjn7z45d1zh0fzncdcf6f7d";
fetchSubmodules = true;
};
rustManifest = ./channel-rust-nightly.toml;
targets = [];
rustChannelOfTargets = _channel: _date: targets:
(pkgs.lib.rustLib.fromManifestFile rustManifest {
inherit (pkgs) stdenv fetchurl patchelf;
}).rust.override { inherit targets; };
rust =
rustChannelOfTargets "nightly" null targets;
in
pkgs.recurseIntoAttrs (pkgs.makeRustPlatform {
rustc = rust // { src = rustcSrc; };
cargo = rust;
})

14
shell.nix
View File

@ -1,12 +1,10 @@
let
zynq-rs = (import ./zynq-rs.nix);
pkgs = import <nixpkgs> { overlays = [ (import "${zynq-rs}/nix/mozilla-overlay.nix") ]; };
rustPlatform = (import "${zynq-rs}/nix/rust-platform.nix" { inherit pkgs; });
mozillaOverlay = import (builtins.fetchTarball "https://github.com/mozilla/nixpkgs-mozilla/archive/master.tar.gz");
pkgs = import <nixpkgs> { overlays = [ mozillaOverlay ]; };
artiq-fast = <artiq-fast>;
rustPlatform = (import ./rustPlatform.nix { inherit pkgs; });
artiqpkgs = import "${artiq-fast}/default.nix" { inherit pkgs; };
vivado = import "${artiq-fast}/vivado.nix" { inherit pkgs; };
cargo-xbuild = import ./cargo-xbuild.nix { inherit pkgs; };
zc706-szl = (import zynq-rs).zc706-szl;
in
pkgs.stdenv.mkDerivation {
name = "artiq-zynq-env";
@ -17,7 +15,7 @@ in
pkgs.llvmPackages_9.llvm
pkgs.llvmPackages_9.clang-unwrapped
pkgs.cacert
cargo-xbuild
pkgs.cargo-xbuild
pkgs.openocd
pkgs.openssh pkgs.rsync
@ -26,10 +24,8 @@ in
vivado
artiqpkgs.binutils-arm
(import "${zynq-rs}/nix/mkbootimage.nix" { inherit pkgs; })
(import ./mkbootimage.nix { inherit pkgs; })
];
XARGO_RUST_SRC = "${rustPlatform.rust.rustc.src}/src";
OPENOCD_ZYNQ = "${zynq-rs}/openocd";
SZL = "${zc706-szl}/szl.elf";
}

131
src/Cargo.lock generated
View File

@ -37,9 +37,9 @@ checksum = "08c48aae112d48ed9f069b33538ea9e3e90aa263cfa3d1c24309612b1f7472de"
[[package]]
name = "cc"
version = "1.0.58"
version = "1.0.57"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "f9a06fb2e53271d7c279ec1efea6ab691c35a2ae67ec0d91d7acec0caf13b518"
checksum = "0fde55d2a2bfaa4c9668bbc63f531fbdeee3ffe188f4662511ce2c22b3eedebe"
[[package]]
name = "cfg-if"
@ -49,16 +49,13 @@ checksum = "4785bdd1c96b2a846b2bd7cc02e86b6b3dbf14e7e53446c4f54c92a361040822"
[[package]]
name = "compiler_builtins"
version = "0.1.33"
source = "git+https://git.m-labs.hk/M-Labs/compiler-builtins-zynq.git#62a622ba62c671aaadce7c108854551086df41f8"
dependencies = [
"cc",
]
version = "0.1.32"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "7bc4ac2c824d2bfc612cba57708198547e9a26943af0632aff033e0693074d5c"
[[package]]
name = "core_io"
version = "0.1.20200410"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#7360984efbd772ae992ef00af09786b0ae8430f0"
dependencies = [
"memchr",
]
@ -69,6 +66,22 @@ version = "0.3.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "0f8cb7306107e4b10e64994de6d3274bd08996a7c1322a27b86482392f96be0a"
[[package]]
name = "cstr_core"
version = "0.2.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "8758514b5f03968703f1db1f1e196e031d5268f5295ff99a5bf345008790ba85"
dependencies = [
"cty",
"memchr",
]
[[package]]
name = "cty"
version = "0.2.1"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "7313c0d620d0cb4dbd9d019e461a4beb501071ff46ec0ab933efb4daa76d73e3"
[[package]]
name = "dwarf"
version = "0.0.0"
@ -83,7 +96,6 @@ dependencies = [
name = "dyld"
version = "0.1.0"
dependencies = [
"libcortex_a9",
"log",
]
@ -93,15 +105,15 @@ version = "0.2.4"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "fa998ce59ec9765d15216393af37a58961ddcefb14c753b4816ba2191d865fcb"
dependencies = [
"nb 0.1.3",
"nb",
"void",
]
[[package]]
name = "fatfs"
version = "0.3.4"
version = "0.3.3"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "93079df23039e52059e1f03b4c29fb0c72da2c792aad91bb2236c9fb81d3592e"
checksum = "f6d1df9e4503954f60504a5ee4fc435cd65cc42e98b2081f7f421be5f2e68e7d"
dependencies = [
"bitflags",
"byteorder",
@ -188,11 +200,11 @@ dependencies = [
[[package]]
name = "libasync"
version = "0.0.0"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#7360984efbd772ae992ef00af09786b0ae8430f0"
source = "git+https://git.m-labs.hk/M-Labs/zc706.git#371e59cef57746e3dd4cae915be7fd3286972822"
dependencies = [
"embedded-hal",
"libcortex_a9",
"nb 0.1.3",
"nb",
"pin-utils",
"smoltcp",
]
@ -200,14 +212,14 @@ dependencies = [
[[package]]
name = "libboard_zynq"
version = "0.0.0"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#7360984efbd772ae992ef00af09786b0ae8430f0"
source = "git+https://git.m-labs.hk/M-Labs/zc706.git#371e59cef57746e3dd4cae915be7fd3286972822"
dependencies = [
"bit_field",
"embedded-hal",
"libcortex_a9",
"libregister",
"log",
"nb 0.1.3",
"nb",
"smoltcp",
"void",
"volatile-register",
@ -221,37 +233,19 @@ dependencies = [
"libboard_zynq",
]
[[package]]
name = "libconfig"
version = "0.1.0"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#7360984efbd772ae992ef00af09786b0ae8430f0"
dependencies = [
"core_io",
"fatfs",
"libboard_zynq",
"log",
]
[[package]]
name = "libcortex_a9"
version = "0.0.0"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#7360984efbd772ae992ef00af09786b0ae8430f0"
source = "git+https://git.m-labs.hk/M-Labs/zc706.git#371e59cef57746e3dd4cae915be7fd3286972822"
dependencies = [
"bit_field",
"libregister",
"volatile-register",
]
[[package]]
name = "libm"
version = "0.2.1"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "c7d73b3f436185384286bd8098d17ec07c9a7d2388a6599f824d8502b529702a"
[[package]]
name = "libregister"
version = "0.0.0"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#7360984efbd772ae992ef00af09786b0ae8430f0"
source = "git+https://git.m-labs.hk/M-Labs/zc706.git#371e59cef57746e3dd4cae915be7fd3286972822"
dependencies = [
"bit_field",
"vcell",
@ -261,7 +255,7 @@ dependencies = [
[[package]]
name = "libsupport_zynq"
version = "0.0.0"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#7360984efbd772ae992ef00af09786b0ae8430f0"
source = "git+https://git.m-labs.hk/M-Labs/zc706.git#371e59cef57746e3dd4cae915be7fd3286972822"
dependencies = [
"compiler_builtins",
"libboard_zynq",
@ -273,15 +267,15 @@ dependencies = [
[[package]]
name = "linked_list_allocator"
version = "0.8.5"
version = "0.8.4"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "660b26e6156a7d00eefb19052fe1943cf5ab2f353a723a577fad6ba2f99d1f90"
checksum = "e70e46c13c0e8374c26cec5752e3347ca1087d9711de8f45aa513a7700efd73d"
[[package]]
name = "log"
version = "0.4.11"
version = "0.4.8"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "4fabed175da42fed1fa0746b0ea71f412aa9d35e76e95e59b192c64b9dc2bf8b"
checksum = "14b6052be84e6b71ab17edffc2eeabf5c2c3ae1fdb464aae35ac50c67a44e1f7"
dependencies = [
"cfg-if",
]
@ -306,24 +300,15 @@ checksum = "3728d817d99e5ac407411fa471ff9800a778d88a24685968b36824eaf4bee400"
[[package]]
name = "nb"
version = "0.1.3"
version = "0.1.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "801d31da0513b6ec5214e9bf433a77966320625a37860f910be265be6e18d06f"
dependencies = [
"nb 1.0.0",
]
[[package]]
name = "nb"
version = "1.0.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "546c37ac5d9e56f55e73b677106873d9d9f5190605e41a856503623648488cae"
checksum = "b1411551beb3c11dedfb0a90a0fa256b47d28b9ec2cdff34c25a2fa59e45dbdc"
[[package]]
name = "num-derive"
version = "0.3.1"
version = "0.3.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "e0396233fb2d5b0ae3f05ff6aba9a09185f7f6e70f87fb01147d545f85364665"
checksum = "0c8b15b261814f992e33760b1fca9fe8b693d8a65299f20c9901688636cfb746"
dependencies = [
"proc-macro2",
"quote",
@ -341,18 +326,18 @@ dependencies = [
[[package]]
name = "pin-project"
version = "0.4.23"
version = "0.4.22"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "ca4433fff2ae79342e497d9f8ee990d174071408f28f726d6d83af93e58e48aa"
checksum = "12e3a6cdbfe94a5e4572812a0201f8c0ed98c1c452c7b8563ce2276988ef9c17"
dependencies = [
"pin-project-internal",
]
[[package]]
name = "pin-project-internal"
version = "0.4.23"
version = "0.4.22"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "2c0e815c3ee9a031fdf5af21c10aa17c573c9c6a566328d99e3936c34e36461f"
checksum = "6a0ffd45cf79d88737d7cc85bfd5d2894bee1139b356e616fe85dc389c61aaf7"
dependencies = [
"proc-macro2",
"quote",
@ -367,9 +352,9 @@ checksum = "8b870d8c151b6f2fb93e84a13146138f05d02ed11c7e7c54f8826aaaf7c9f184"
[[package]]
name = "proc-macro-hack"
version = "0.5.18"
version = "0.5.16"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "99c605b9a0adc77b7211c6b1f722dcb613d68d66859a44f3d485a6da332b0598"
checksum = "7e0456befd48169b9f13ef0f0ad46d492cf9d2dbb918bcf38e01eed4ce3ec5e4"
[[package]]
name = "proc-macro-nested"
@ -379,9 +364,9 @@ checksum = "eba180dafb9038b050a4c280019bbedf9f2467b61e5d892dcad585bb57aadc5a"
[[package]]
name = "proc-macro2"
version = "1.0.19"
version = "1.0.18"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "04f5f085b5d71e2188cb8271e5da0161ad52c3f227a661a3c135fdf28e258b12"
checksum = "beae6331a816b1f65d04c45b078fd8e6c93e8071771f41b8163255bbd8d7c8fa"
dependencies = [
"unicode-xid",
]
@ -412,22 +397,20 @@ dependencies = [
"dwarf",
"dyld",
"embedded-hal",
"fatfs",
"futures",
"libasync",
"libboard_zynq",
"libc",
"libconfig",
"libcortex_a9",
"libm",
"libregister",
"libsupport_zynq",
"log",
"log_buffer",
"nb 0.1.3",
"nb",
"num-derive",
"num-traits",
"unwind",
"vcell",
"void",
]
@ -444,15 +427,27 @@ dependencies = [
[[package]]
name = "syn"
version = "1.0.38"
version = "1.0.33"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "e69abc24912995b3038597a7a593be5053eb0fb44f3cc5beec0deb421790c1f4"
checksum = "e8d5d96e8cbb005d6959f119f773bfaebb5684296108fb32600c00cde305b2cd"
dependencies = [
"proc-macro2",
"quote",
"unicode-xid",
]
[[package]]
name = "szl"
version = "0.1.0"
dependencies = [
"cc",
"cstr_core",
"libboard_zynq",
"libcortex_a9",
"libsupport_zynq",
"log",
]
[[package]]
name = "unicode-xid"
version = "0.2.1"

14
src/Cargo.toml
View File

@ -2,18 +2,24 @@
members = [
"libc",
"libdyld",
"libcoreio",
"libdwarf",
"libunwind",
"runtime",
"szl"
]
[profile.dev]
panic = "abort"
lto = false
[profile.release]
panic = "abort"
debug = true
codegen-units = 1
opt-level = 2
# Link-Time Optimization:
# turn off if you get unusable debug symbols.
lto = true
opt-level = 'z' # Optimize for size.
[patch.crates-io]
core_io = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
compiler_builtins = { git = "https://git.m-labs.hk/M-Labs/compiler-builtins-zynq.git"}
core_io = { path = "./libcoreio" }

16
src/Makefile
View File

@ -1,16 +1,20 @@
VARIANT := simple
all: ../build/firmware/armv7-none-eabihf/release/runtime ../build/runtime.bin
all: ../build/firmware/armv7-none-eabihf/release/szl
.PHONY: all
../build/pl.rs ../build/rustc-cfg: gateware/*
../build/pl.rs: zc706.py
mkdir -p ../build
python gateware/zc706.py -r ../build/pl.rs -c ../build/rustc-cfg -V $(VARIANT)
python zc706.py -r ../build/pl.rs -V $(VARIANT)
../build/firmware/armv7-none-eabihf/release/runtime: ../build/pl.rs ../build/rustc-cfg $(shell find . -path ./szl -prune -o -print)
../build/firmware/armv7-none-eabihf/release/runtime: ../build/pl.rs $(shell find . -path ./szl -prune -o -print)
XBUILD_SYSROOT_PATH=`pwd`/../build/sysroot cargo xbuild --release -p runtime --target-dir ../build/firmware
../build/runtime.bin: ../build/firmware/armv7-none-eabihf/release/runtime
llvm-objcopy -O binary ../build/firmware/armv7-none-eabihf/release/runtime ../build/runtime.bin
../build/szl-payload.bin.lzma: ../build/firmware/armv7-none-eabihf/release/runtime
llvm-objcopy -O binary ../build/firmware/armv7-none-eabihf/release/runtime ../build/szl-payload.bin
lzma --keep -f ../build/szl-payload.bin
../build/firmware/armv7-none-eabihf/release/szl: .cargo/* armv7-none-eabihf.json Cargo.lock Cargo.toml szl/* szl/src/* ../build/szl-payload.bin.lzma
XBUILD_SYSROOT_PATH=`pwd`/../build/sysroot cargo xbuild --release -p szl --target-dir ../build/firmware

272
src/gateware/acpki.py
View File

@ -1,272 +0,0 @@
from operator import attrgetter
from migen import *
from migen.genlib.cdc import MultiReg
from migen_axi.interconnect import axi
from misoc.interconnect.csr import *
from artiq.gateware import rtio
OUT_BURST_LEN = 10
IN_BURST_LEN = 4
class Engine(Module, AutoCSR):
def __init__(self, bus, user):
self.addr_base = CSRStorage(32)
self.trig_count = CSRStatus(32)
self.write_count = CSRStatus(32)
self.trigger_stb = Signal()
# Dout : Data received from CPU, output by DMA module
# Din : Data driven into DMA module, written into CPU
# When stb assert, index shows word being read/written, dout/din holds
# data
#
# Cycle:
# trigger_stb pulsed at start
# Then out_burst_len words are strobed out of dout
# Then, when din_ready is high, in_burst_len words are strobed in to din
self.dout_stb = Signal()
self.din_stb = Signal()
self.dout_index = Signal(max=16)
self.din_index = Signal(max=16)
self.din_ready = Signal()
self.dout = Signal(64)
self.din = Signal(64)
###
self.sync += If(self.trigger_stb, self.trig_count.status.eq(self.trig_count.status+1))
self.comb += [
user.aruser.eq(0x1f),
user.awuser.eq(0x1f)
]
ar, aw, w, r, b = attrgetter("ar", "aw", "w", "r", "b")(bus)
### Read
self.comb += [
ar.addr.eq(self.addr_base.storage),
self.dout.eq(r.data),
r.ready.eq(1),
ar.burst.eq(axi.Burst.incr.value),
ar.len.eq(OUT_BURST_LEN-1), # Number of transfers in burst (0->1 transfer, 1->2 transfers...)
ar.size.eq(3), # Width of burst: 3 = 8 bytes = 64 bits
ar.cache.eq(0xf),
]
# read control
self.submodules.read_fsm = read_fsm = FSM(reset_state="IDLE")
read_fsm.act("IDLE",
If(self.trigger_stb,
ar.valid.eq(1),
If(ar.ready,
NextState("READ")
).Else(
NextState("READ_START")
)
)
)
read_fsm.act("READ_START",
ar.valid.eq(1),
If(ar.ready,
NextState("READ"),
)
)
read_fsm.act("READ",
ar.valid.eq(0),
If(r.last & r.valid,
NextState("IDLE")
)
)
self.sync += [
If(read_fsm.ongoing("IDLE"),
self.dout_index.eq(0)
).Else(If(r.valid & read_fsm.ongoing("READ"),
self.dout_index.eq(self.dout_index+1)
)
)
]
self.comb += self.dout_stb.eq(r.valid & r.ready)
### Write
self.comb += [
w.data.eq(self.din),
aw.addr.eq(self.addr_base.storage+96),
w.strb.eq(0xff),
aw.burst.eq(axi.Burst.incr.value),
aw.len.eq(IN_BURST_LEN-1), # Number of transfers in burst minus 1
aw.size.eq(3), # Width of burst: 3 = 8 bytes = 64 bits
aw.cache.eq(0xf),
b.ready.eq(1),
]
# write control
self.submodules.write_fsm = write_fsm = FSM(reset_state="IDLE")
write_fsm.act("IDLE",
w.valid.eq(0),
aw.valid.eq(0),
If(self.trigger_stb,
aw.valid.eq(1),
If(aw.ready, # assumes aw.ready is not randomly deasserted
NextState("DATA_WAIT")
).Else(
NextState("AW_READY_WAIT")
)
)
)
write_fsm.act("AW_READY_WAIT",
aw.valid.eq(1),
If(aw.ready,
NextState("DATA_WAIT"),
)
)
write_fsm.act("DATA_WAIT",
aw.valid.eq(0),
If(self.din_ready,
w.valid.eq(1),
NextState("WRITE")
)
)
write_fsm.act("WRITE",
w.valid.eq(1),
If(w.ready & w.last,
NextState("IDLE")
)
)
self.sync += If(w.ready & w.valid, self.write_count.status.eq(self.write_count.status+1))
self.sync += [
If(write_fsm.ongoing("IDLE"),
self.din_index.eq(0)
),
If(w.ready & w.valid, self.din_index.eq(self.din_index+1))
]
self.comb += [
w.last.eq(0),
If(self.din_index==aw.len, w.last.eq(1))
]
self.comb += self.din_stb.eq(w.valid & w.ready)
class KernelInitiator(Module, AutoCSR):
def __init__(self, tsc, bus, user, evento):
# Core is disabled upon reset to avoid spurious triggering if evento toggles from e.g. boot code.
self.enable = CSRStorage()
self.counter = CSRStatus(64)
self.counter_update = CSR()
self.o_status = CSRStatus(3)
self.i_status = CSRStatus(4)
self.submodules.engine = Engine(bus, user)
self.cri = rtio.cri.Interface()
###
evento_stb = Signal()
evento_latched = Signal()
evento_latched_d = Signal()
self.specials += MultiReg(evento, evento_latched)
self.sync += evento_latched_d.eq(evento_latched)
self.comb += self.engine.trigger_stb.eq(self.enable.storage & (evento_latched != evento_latched_d))
cri = self.cri
cmd = Signal(8)
cmd_write = Signal()
cmd_read = Signal()
self.comb += [
cmd_write.eq(cmd == 0),
cmd_read.eq(cmd == 1)
]
out_len = Signal(8)
dout_cases = {}
dout_cases[0] = [
cmd.eq(self.engine.dout[:8]),
out_len.eq(self.engine.dout[8:16]),
cri.chan_sel.eq(self.engine.dout[40:]),
cri.o_address.eq(self.engine.dout[32:40])
]
for i in range(8):
target = cri.o_data[i*64:(i+1)*64]
dout_cases[0] += [If(i >= self.engine.dout[8:16], target.eq(0))]
dout_cases[1] = [
cri.o_timestamp.eq(self.engine.dout),
cri.i_timeout.eq(self.engine.dout)
]
for i in range(8):
target = cri.o_data[i*64:(i+1)*64]
dout_cases[i+2] = [target.eq(self.engine.dout)]
self.sync += [
cri.cmd.eq(rtio.cri.commands["nop"]),
If(self.engine.dout_stb,
Case(self.engine.dout_index, dout_cases),
If(self.engine.dout_index == out_len + 2,
If(cmd_write, cri.cmd.eq(rtio.cri.commands["write"])),
If(cmd_read, cri.cmd.eq(rtio.cri.commands["read"]))
)
)
]
# If input event, wait for response before allow input data to be
# sampled
# TODO: If output, wait for wait flag clear
RTIO_I_STATUS_WAIT_STATUS = 4
RTIO_O_STATUS_WAIT = 1
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
If(self.engine.trigger_stb, NextState("WAIT_OUT_CYCLE"))
)
fsm.act("WAIT_OUT_CYCLE",
self.engine.din_ready.eq(0),
If(self.engine.dout_stb & cmd_write & (self.engine.dout_index == out_len + 2),
NextState("WAIT_READY")
),
# for some reason read requires some delay until the next state
If(self.engine.dout_stb & cmd_read & (self.engine.dout_index == out_len + 3),
NextState("WAIT_READY")
)
)
fsm.act("WAIT_READY",
If(cmd_read & (cri.i_status & RTIO_I_STATUS_WAIT_STATUS == 0) \
| cmd_write & ~(cri.o_status & RTIO_O_STATUS_WAIT),
self.engine.din_ready.eq(1),
NextState("IDLE")
)
)
din_cases_cmdwrite = {
0: [self.engine.din.eq((1<<16) | cri.o_status)],
1: [self.engine.din.eq(0)],
}
din_cases_cmdread = {
0: [self.engine.din[:32].eq((1<<16) | cri.i_status), self.engine.din[32:].eq(cri.i_data)],
1: [self.engine.din.eq(cri.i_timestamp)]
}
self.comb += [
If(cmd_read, Case(self.engine.din_index, din_cases_cmdread)),
If(cmd_write, Case(self.engine.din_index, din_cases_cmdwrite)),
]
# CRI CSRs
self.sync += If(self.counter_update.re, self.counter.status.eq(tsc.full_ts_cri))
self.comb += [
self.o_status.status.eq(self.cri.o_status),
self.i_status.status.eq(self.cri.i_status),
]

121
src/gateware/analyzer.py
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@ -1,121 +0,0 @@
from migen import *
from misoc.interconnect.csr import *
from misoc.interconnect import stream
from migen_axi.interconnect import axi
from artiq.gateware.rtio.analyzer import message_len, MessageEncoder
import endianness
class AXIDMAWriter(Module, AutoCSR):
def __init__(self, membus, max_outstanding_requests):
aw = len(membus.aw.addr)
dw = len(membus.w.data)
assert message_len % dw == 0
burst_length = message_len//dw
alignment_bits = log2_int(message_len//8)
self.reset = CSR() # only apply when shut down
# All numbers in bytes
self.base_address = CSRStorage(aw, alignment_bits=alignment_bits)
self.last_address = CSRStorage(aw, alignment_bits=alignment_bits)
self.byte_count = CSRStatus(32) # only read when shut down
self.bus_error = CSRStatus()
self.make_request = Signal()
self.sink = stream.Endpoint([("data", dw)])
# # #
outstanding_requests = Signal(max=max_outstanding_requests+1)
current_address = Signal(aw - alignment_bits)
self.comb += [
membus.aw.addr.eq(Cat(C(0, alignment_bits), current_address)),
membus.aw.id.eq(0), # Same ID for all transactions to forbid reordering.
membus.aw.burst.eq(axi.Burst.incr.value),
membus.aw.len.eq(burst_length-1), # Number of transfers in burst (0->1 transfer, 1->2 transfers...).
membus.aw.size.eq(log2_int(dw//8)), # Width of burst: 3 = 8 bytes = 64 bits.
membus.aw.cache.eq(0xf),
membus.aw.valid.eq(outstanding_requests != 0),
]
self.sync += [
outstanding_requests.eq(outstanding_requests + self.make_request - (membus.aw.valid & membus.aw.ready)),
If(self.reset.re,
current_address.eq(self.base_address.storage)),
If(membus.aw.valid & membus.aw.ready,
If(current_address == self.last_address.storage,
current_address.eq(self.base_address.storage)
).Else(
current_address.eq(current_address + 1)
)
)
]
self.comb += [
membus.w.id.eq(0),
membus.w.valid.eq(self.sink.stb),
self.sink.ack.eq(membus.w.ready),
membus.w.data.eq(endianness.convert_signal(self.sink.data)),
membus.w.strb.eq(2**(dw//8)-1),
]
beat_count = Signal(max=burst_length)
self.sync += [
If(membus.w.valid & membus.w.ready,
membus.w.last.eq(0),
If(membus.w.last,
beat_count.eq(0)
).Else(
If(beat_count == burst_length-2, membus.w.last.eq(1)),
beat_count.eq(beat_count + 1)
)
)
]
message_count = Signal(32 - log2_int(message_len//8))
self.comb += self.byte_count.status.eq(
message_count << log2_int(message_len//8))
self.sync += [
If(self.reset.re, message_count.eq(0)),
If(membus.w.valid & membus.w.ready & membus.w.last, message_count.eq(message_count + 1))
]
self.comb += membus.b.ready.eq(1)
self.sync += [
If(self.reset.re, self.bus_error.status.eq(0)),
If(membus.b.valid & membus.b.ready & (membus.b.resp != axi.Response.okay),
self.bus_error.status.eq(1))
]
class Analyzer(Module, AutoCSR):
def __init__(self, tsc, cri, membus, fifo_depth=128):
# shutdown procedure: set enable to 0, wait until busy=0
self.enable = CSRStorage()
self.busy = CSRStatus()
self.submodules.message_encoder = MessageEncoder(
tsc, cri, self.enable.storage)
self.submodules.fifo = stream.SyncFIFO(
[("data", message_len)], fifo_depth, True)
self.submodules.converter = stream.Converter(
message_len, len(membus.w.data), reverse=True)
self.submodules.dma = AXIDMAWriter(membus, max_outstanding_requests=fifo_depth)
enable_r = Signal()
self.sync += [
enable_r.eq(self.enable.storage),
If(self.enable.storage & ~enable_r,
self.busy.status.eq(1)),
If(self.dma.sink.stb & self.dma.sink.ack & self.dma.sink.eop,
self.busy.status.eq(0))
]
self.comb += [
self.message_encoder.source.connect(self.fifo.sink),
self.fifo.source.connect(self.converter.sink),
self.converter.source.connect(self.dma.sink),
self.dma.make_request.eq(self.fifo.sink.stb & self.fifo.sink.ack)
]

157
src/gateware/dma.py
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@ -1,157 +0,0 @@
from migen import *
from migen.genlib.fsm import FSM
from misoc.interconnect.csr import *
from misoc.interconnect import stream
from migen_axi.interconnect import axi
from artiq.gateware.rtio.dma import RawSlicer, RecordConverter, RecordSlicer, TimeOffset, CRIMaster
import endianness
AXI_BURST_LEN = 16
class AXIReader(Module, AutoCSR):
def __init__(self, membus):
aw = len(membus.ar.addr)
dw = len(membus.r.data)
alignment_bits = log2_int(AXI_BURST_LEN*dw//8)
self.sink = stream.Endpoint([("address", aw - alignment_bits)])
self.source = stream.Endpoint([("data", dw)])
self.bus_error = CSRStatus()
# # #
eop_pending = Signal()
self.sync += [
If(self.sink.stb & self.sink.ack & self.sink.eop, eop_pending.eq(1)),
If(self.source.stb & self.source.ack & self.source.eop, eop_pending.eq(0)),
]
self.comb += [
membus.ar.addr.eq(Cat(C(0, alignment_bits), self.sink.address)),
membus.ar.id.eq(0), # Same ID for all transactions to forbid reordering.
membus.ar.burst.eq(axi.Burst.incr.value),
membus.ar.len.eq(AXI_BURST_LEN-1), # Number of transfers in burst (0->1 transfer, 1->2 transfers...).
membus.ar.size.eq(log2_int(dw//8)), # Width of burst: 3 = 8 bytes = 64 bits.
membus.ar.cache.eq(0xf),
membus.ar.valid.eq(self.sink.stb & ~eop_pending),
self.sink.ack.eq(membus.ar.ready & ~eop_pending)
]
# UG585: "Large slave interface read acceptance capability in the range of 14 to 70 commands"
inflight_cnt = Signal(max=128)
request_done = Signal()
reply_done = Signal()
self.comb += [
request_done.eq(membus.ar.valid & membus.ar.ready),
reply_done.eq(membus.r.valid & membus.r.ready & membus.r.last)
]
self.sync += inflight_cnt.eq(inflight_cnt + request_done - reply_done)
self.comb += [
self.source.stb.eq(membus.r.valid),
membus.r.ready.eq(self.source.ack),
self.source.data.eq(endianness.convert_signal(membus.r.data)),
# Note that when eop_pending=1, no new transactions are made and inflight_cnt is no longer incremented
self.source.eop.eq(eop_pending & membus.r.last & (inflight_cnt == 1))
]
stopped = Signal(reset=1)
self.sync += [
If(self.source.stb & self.source.ack & self.source.eop, stopped.eq(1)),
If(self.sink.stb & self.sink.ack, stopped.eq(0)),
If(stopped & (self.sink.stb & self.sink.ack),
# reset bus error status on new run
self.bus_error.status.eq(0)),
If(membus.r.valid & membus.r.valid & (membus.r.resp != axi.Response.okay),
self.bus_error.status.eq(1))
]
class DMAReader(Module, AutoCSR):
def __init__(self, membus, enable):
aw = len(membus.ar.addr)
alignment_bits = log2_int(AXI_BURST_LEN*len(membus.r.data)//8)
self.submodules.wb_reader = AXIReader(membus)
self.source = self.wb_reader.source
# All numbers in bytes
self.base_address = CSRStorage(aw, alignment_bits=alignment_bits)
# # #
enable_r = Signal()
address = self.wb_reader.sink
assert len(address.address) == len(self.base_address.storage)
self.sync += [
enable_r.eq(enable),
If(enable & ~enable_r,
address.address.eq(self.base_address.storage),
address.eop.eq(0),
address.stb.eq(1),
),
If(address.stb & address.ack,
If(address.eop,
address.stb.eq(0)
).Else(
address.address.eq(address.address + 1),
If(~enable, address.eop.eq(1))
)
)
]
class DMA(Module):
def __init__(self, membus):
self.enable = CSR()
flow_enable = Signal()
self.submodules.dma = DMAReader(membus, flow_enable)
self.submodules.slicer = RecordSlicer(len(membus.r.data))
self.submodules.time_offset = TimeOffset()
self.submodules.cri_master = CRIMaster()
self.cri = self.cri_master.cri
self.comb += [
self.dma.source.connect(self.slicer.sink),
self.slicer.source.connect(self.time_offset.sink),
self.time_offset.source.connect(self.cri_master.sink)
]
fsm = FSM(reset_state="IDLE")
self.submodules += fsm
fsm.act("IDLE",
If(self.enable.re, NextState("FLOWING"))
)
fsm.act("FLOWING",
self.enable.w.eq(1),
flow_enable.eq(1),
If(self.slicer.end_marker_found,
NextState("FLUSH")
)
)
fsm.act("FLUSH",
self.enable.w.eq(1),
self.slicer.flush.eq(1),
NextState("WAIT_EOP")
)
fsm.act("WAIT_EOP",
self.enable.w.eq(1),
If(self.cri_master.sink.stb & self.cri_master.sink.ack & self.cri_master.sink.eop,
NextState("WAIT_CRI_MASTER")
)
)
fsm.act("WAIT_CRI_MASTER",
self.enable.w.eq(1),
If(~self.cri_master.busy, NextState("IDLE"))
)
def get_csrs(self):
return ([self.enable] +
self.dma.get_csrs() + self.time_offset.get_csrs() +
self.cri_master.get_csrs())

21
src/gateware/endianness.py
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@ -1,21 +0,0 @@
from migen import *
def convert_signal(signal):
assert len(signal) % 8 == 0
nbytes = len(signal)//8
signal_bytes = []
for i in range(nbytes):
signal_bytes.append(signal[8*i:8*(i+1)])
return Cat(*reversed(signal_bytes))
def convert_value(value, size):
assert size % 8 == 0
nbytes = size//8
result = 0
for i in range(nbytes):
result <<= 8
result |= value & 0xff
value >>= 8
return result

236
src/gateware/test_dma.py
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@ -1,236 +0,0 @@
import unittest
import random
import itertools
from migen import *
from migen_axi.interconnect import axi
from artiq.coredevice.exceptions import RTIOUnderflow, RTIODestinationUnreachable
from artiq.gateware import rtio
from artiq.gateware.rtio import cri
from artiq.gateware.rtio.phy import ttl_simple
import endianness
import dma
class AXIMemorySim:
def __init__(self, bus, data, max_queue=12):
self.bus = bus
self.data = data
self.max_queue = max_queue
self.align = len(bus.r.data)//8
self.queue = []
@passive
def ar(self):
while True:
if len(self.queue) < self.max_queue:
request = yield from self.bus.read_ar()
self.queue.append(request)
else:
yield
@passive
def r(self):
while True:
if self.queue:
request = self.queue.pop()
if request.burst:
request_len = request.len + 1
else:
request_len = 1
for i in range(request_len):
if request.addr % self.align:
raise ValueError
addr = request.addr//self.align + i
if addr < len(self.data):
data = self.data[addr]
else:
data = 0
data = endianness.convert_value(data, len(self.bus.r.data))
yield from self.bus.write_r(request.id, data, last=i == request_len-1)
else:
yield
def encode_n(n, min_length, max_length):
r = []
while n:
r.append(n & 0xff)
n >>= 8
r += [0]*(min_length - len(r))
if len(r) > max_length:
raise ValueError
return r
def encode_record(channel, timestamp, address, data):
r = []
r += encode_n(channel, 3, 3)
r += encode_n(timestamp, 8, 8)
r += encode_n(address, 1, 1)
r += encode_n(data, 1, 64)
return encode_n(len(r)+1, 1, 1) + r
def pack(x, size):
r = []
for i in range((len(x)+size-1)//size):
n = 0
for j in range(i*size, (i+1)*size):
n <<= 8
try:
n |= x[j]
except IndexError:
pass
r.append(n)
return r
def encode_sequence(writes, ws):
sequence = [b for write in writes for b in encode_record(*write)]
sequence.append(0)
return pack(sequence, ws)
def do_dma(dut, address):
yield from dut.dma.base_address.write(address)
yield from dut.enable.write(1)
yield
while ((yield from dut.enable.read())):
yield
error = yield from dut.cri_master.error.read()
if error & 1:
raise RTIOUnderflow
if error & 2:
raise RTIODestinationUnreachable
test_writes1 = [
(0x01, 0x23, 0x12, 0x33),
(0x901, 0x902, 0x11, 0xeeeeeeeeeeeeeefffffffffffffffffffffffffffffff28888177772736646717738388488),
(0x81, 0x288, 0x88, 0x8888)
]
test_writes2 = [
(0x10, 0x10000, 0x20, 0x77),
(0x11, 0x10001, 0x22, 0x7777),
(0x12, 0x10002, 0x30, 0x777777),
(0x13, 0x10003, 0x40, 0x77777788),
(0x14, 0x10004, 0x50, 0x7777778899),
]
prng = random.Random(0)
class TB(Module):
def __init__(self, ws):
sequence1 = encode_sequence(test_writes1, ws)
sequence2 = encode_sequence(test_writes2, ws)
offset = 512//ws
assert len(sequence1) < offset
sequence = (
sequence1 +
[prng.randrange(2**(ws*8)) for _ in range(offset-len(sequence1))] +
sequence2)
bus = axi.Interface(ws*8)
self.memory = AXIMemorySim(bus, sequence)
self.submodules.dut = dma.DMA(bus)
test_writes_full_stack = [
(0, 32, 0, 1),
(1, 40, 0, 1),
(0, 48, 0, 0),
(1, 50, 0, 0),
]
class FullStackTB(Module):
def __init__(self, ws):
self.ttl0 = Signal()
self.ttl1 = Signal()
self.submodules.phy0 = ttl_simple.Output(self.ttl0)
self.submodules.phy1 = ttl_simple.Output(self.ttl1)
rtio_channels = [
rtio.Channel.from_phy(self.phy0),
rtio.Channel.from_phy(self.phy1)
]
sequence = encode_sequence(test_writes_full_stack, ws)
bus = axi.Interface(ws*8)
self.memory = AXIMemorySim(bus, sequence)
self.submodules.dut = dma.DMA(bus)
self.submodules.tsc = rtio.TSC("async")
self.submodules.rtio = rtio.Core(self.tsc, rtio_channels)
self.comb += self.dut.cri.connect(self.rtio.cri)
class TestDMA(unittest.TestCase):
def test_dma_noerror(self):
tb = TB(8)
def do_writes():
yield from do_dma(tb.dut, 0)
yield from do_dma(tb.dut, 512)
received = []
@passive
def rtio_sim():
dut_cri = tb.dut.cri
while True:
cmd = yield dut_cri.cmd
if cmd == cri.commands["nop"]:
pass
elif cmd == cri.commands["write"]:
channel = yield dut_cri.chan_sel
timestamp = yield dut_cri.o_timestamp
address = yield dut_cri.o_address
data = yield dut_cri.o_data
received.append((channel, timestamp, address, data))
yield dut_cri.o_status.eq(1)
for i in range(prng.randrange(10)):
yield
yield dut_cri.o_status.eq(0)
else:
self.fail("unexpected RTIO command")
yield
run_simulation(tb, [do_writes(), rtio_sim(), tb.memory.ar(), tb.memory.r()])
self.assertEqual(received, test_writes1 + test_writes2)
def test_full_stack(self):
tb = FullStackTB(8)
ttl_changes = []
@passive
def monitor():
old_ttl_states = [0, 0]
for time in itertools.count():
ttl_states = [
(yield tb.ttl0),
(yield tb.ttl1)
]
for i, (old, new) in enumerate(zip(old_ttl_states, ttl_states)):
if new != old:
ttl_changes.append((time, i))
old_ttl_states = ttl_states
yield
run_simulation(tb, {"sys": [
do_dma(tb.dut, 0), monitor(),
(None for _ in range(70)),
tb.memory.ar(), tb.memory.r()
]}, {"sys": 8, "rsys": 8, "rtio": 8, "rio": 8, "rio_phy": 8})
correct_changes = [(timestamp + 11, channel)
for channel, timestamp, _, _ in test_writes_full_stack]
self.assertEqual(ttl_changes, correct_changes)

6
src/libc/Cargo.toml
View File

@ -1,12 +1,14 @@
[package]
name = "libc"
version = "0.1.0"
authors = ["M-Labs"]
authors = ["pca006132 <john.lck40@gmail.com>"]
edition = "2018"
build = "build.rs"
# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
[dependencies]
libboard_zynq = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
libboard_zynq = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
[build-dependencies]
cc = { version = "1.0.1" }

2
src/libc/src/lib.rs
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@ -4,9 +4,7 @@
use libboard_zynq::stdio;
pub type c_char = i8;
pub type c_int = i32;
pub type size_t = usize;
pub type uintptr_t = usize;
pub type c_void = core::ffi::c_void;

14
src/libcoreio/Cargo.toml Normal file
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@ -0,0 +1,14 @@
[package]
authors = ["M-Labs"]
name = "core_io"
version = "0.1.20200410"
[lib]
name = "core_io"
[dependencies]
memchr = { version = "2", default-features = false, optional = true }
[features]
alloc = []
collections = ["alloc", "memchr"]

1674
src/libcoreio/src/io/buffered.rs Normal file
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896
src/libcoreio/src/io/cursor.rs Normal file
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@ -0,0 +1,896 @@
use crate::io::prelude::*;
use core::cmp;
use crate::io::{self, Error, ErrorKind, Initializer, SeekFrom};
#[cfg(feature = "collections")]
use core::convert::TryInto;
#[cfg(feature="collections")]
use collections::vec::Vec;
#[cfg(feature = "alloc")]
use alloc::boxed::Box;
/// A `Cursor` wraps an in-memory buffer and provides it with a
/// [`Seek`] implementation.
///
/// `Cursor`s are used with in-memory buffers, anything implementing
/// `AsRef<[u8]>`, to allow them to implement [`Read`] and/or [`Write`],
/// allowing these buffers to be used anywhere you might use a reader or writer
/// that does actual I/O.
///
/// The standard library implements some I/O traits on various types which
/// are commonly used as a buffer, like `Cursor<`[`Vec`]`<u8>>` and
/// `Cursor<`[`&[u8]`][bytes]`>`.
///
/// # Examples
///
/// We may want to write bytes to a [`File`] in our production
/// code, but use an in-memory buffer in our tests. We can do this with
/// `Cursor`:
///
/// [`Seek`]: trait.Seek.html
/// [`Read`]: ../../std/io/trait.Read.html
/// [`Write`]: ../../std/io/trait.Write.html
/// [`Vec`]: ../../std/vec/struct.Vec.html
/// [bytes]: ../../std/primitive.slice.html
/// [`File`]: ../fs/struct.File.html
///
/// ```no_run
/// use std::io::prelude::*;
/// use std::io::{self, SeekFrom};
/// use std::fs::File;
///
/// // a library function we've written
/// fn write_ten_bytes_at_end<W: Write + Seek>(writer: &mut W) -> io::Result<()> {
/// writer.seek(SeekFrom::End(-10))?;
///
/// for i in 0..10 {
/// writer.write(&[i])?;
/// }
///
/// // all went well
/// Ok(())
/// }
///
/// # fn foo() -> io::Result<()> {
/// // Here's some code that uses this library function.
/// //
/// // We might want to use a BufReader here for efficiency, but let's
/// // keep this example focused.
/// let mut file = File::create("foo.txt")?;
///
/// write_ten_bytes_at_end(&mut file)?;
/// # Ok(())
/// # }
///
/// // now let's write a test
/// #[test]
/// fn test_writes_bytes() {
/// // setting up a real File is much slower than an in-memory buffer,
/// // let's use a cursor instead
/// use std::io::Cursor;
/// let mut buff = Cursor::new(vec![0; 15]);
///
/// write_ten_bytes_at_end(&mut buff).unwrap();
///
/// assert_eq!(&buff.get_ref()[5..15], &[0, 1, 2, 3, 4, 5, 6, 7, 8, 9]);
/// }
/// ```
#[derive(Clone, Debug, Default, Eq, PartialEq)]
pub struct Cursor<T> {
inner: T,
pos: u64,
}
impl<T> Cursor<T> {
/// Creates a new cursor wrapping the provided underlying in-memory buffer.
///
/// Cursor initial position is `0` even if underlying buffer (e.g., `Vec`)
/// is not empty. So writing to cursor starts with overwriting `Vec`
/// content, not with appending to it.
///
/// # Examples
///
/// ```
/// use std::io::Cursor;
///
/// let buff = Cursor::new(Vec::new());
/// # fn force_inference(_: &Cursor<Vec<u8>>) {}
/// # force_inference(&buff);
/// ```
pub fn new(inner: T) -> Cursor<T> {
Cursor { pos: 0, inner }
}
/// Consumes this cursor, returning the underlying value.
///
/// # Examples
///
/// ```
/// use std::io::Cursor;
///
/// let buff = Cursor::new(Vec::new());
/// # fn force_inference(_: &Cursor<Vec<u8>>) {}
/// # force_inference(&buff);
///
/// let vec = buff.into_inner();
/// ```
pub fn into_inner(self) -> T {
self.inner
}
/// Gets a reference to the underlying value in this cursor.
///
/// # Examples
///
/// ```
/// use std::io::Cursor;
///
/// let buff = Cursor::new(Vec::new());
/// # fn force_inference(_: &Cursor<Vec<u8>>) {}
/// # force_inference(&buff);
///
/// let reference = buff.get_ref();
/// ```
pub fn get_ref(&self) -> &T {
&self.inner
}
/// Gets a mutable reference to the underlying value in this cursor.
///
/// Care should be taken to avoid modifying the internal I/O state of the
/// underlying value as it may corrupt this cursor's position.
///
/// # Examples
///
/// ```
/// use std::io::Cursor;
///
/// let mut buff = Cursor::new(Vec::new());
/// # fn force_inference(_: &Cursor<Vec<u8>>) {}
/// # force_inference(&buff);
///
/// let reference = buff.get_mut();
/// ```
pub fn get_mut(&mut self) -> &mut T {
&mut self.inner
}
/// Returns the current position of this cursor.
///
/// # Examples
///
/// ```
/// use std::io::Cursor;
/// use std::io::prelude::*;
/// use std::io::SeekFrom;
///
/// let mut buff = Cursor::new(vec![1, 2, 3, 4, 5]);
///
/// assert_eq!(buff.position(), 0);
///
/// buff.seek(SeekFrom::Current(2)).unwrap();
/// assert_eq!(buff.position(), 2);
///
/// buff.seek(SeekFrom::Current(-1)).unwrap();
/// assert_eq!(buff.position(), 1);
/// ```
pub fn position(&self) -> u64 {
self.pos
}
/// Sets the position of this cursor.
///
/// # Examples
///
/// ```
/// use std::io::Cursor;
///
/// let mut buff = Cursor::new(vec![1, 2, 3, 4, 5]);
///
/// assert_eq!(buff.position(), 0);
///
/// buff.set_position(2);
/// assert_eq!(buff.position(), 2);
///
/// buff.set_position(4);
/// assert_eq!(buff.position(), 4);
/// ```
pub fn set_position(&mut self, pos: u64) {
self.pos = pos;
}
}
impl<T> io::Seek for Cursor<T>
where
T: AsRef<[u8]>,
{
fn seek(&mut self, style: SeekFrom) -> io::Result<u64> {
let (base_pos, offset) = match style {
SeekFrom::Start(n) => {
self.pos = n;
return Ok(n);
}
SeekFrom::End(n) => (self.inner.as_ref().len() as u64, n),
SeekFrom::Current(n) => (self.pos, n),
};
let new_pos = if offset >= 0 {
base_pos.checked_add(offset as u64)
} else {
base_pos.checked_sub((offset.wrapping_neg()) as u64)
};
match new_pos {
Some(n) => {
self.pos = n;
Ok(self.pos)
}
None => Err(Error::new(
ErrorKind::InvalidInput,
"invalid seek to a negative or overflowing position",
)),
}
}
fn stream_len(&mut self) -> io::Result<u64> {
Ok(self.inner.as_ref().len() as u64)
}
fn stream_position(&mut self) -> io::Result<u64> {
Ok(self.pos)
}
}
impl<T> Read for Cursor<T>
where
T: AsRef<[u8]>,
{
fn read(&mut self, buf: &mut [u8]) -> io::Result<usize> {
let n = Read::read(&mut self.get_ref().as_ref(), buf)?;
self.pos += n as u64;
Ok(n)
}
fn read_exact(&mut self, buf: &mut [u8]) -> io::Result<()> {
let n = buf.len();
Read::read_exact(&mut self.get_ref().as_ref(), buf)?;
self.pos += n as u64;
Ok(())
}
#[inline]
unsafe fn initializer(&self) -> Initializer {
Initializer::nop()
}
}
#[cfg(feature = "collections")]
impl<T> BufRead for Cursor<T>
where
T: AsRef<[u8]>,
{
fn fill_buf(&mut self) -> io::Result<&[u8]> {
let amt = cmp::min(self.pos, self.inner.as_ref().len() as u64);
Ok(&self.inner.as_ref()[(amt as usize)..])
}
fn consume(&mut self, amt: usize) {
self.pos += amt as u64;
}
}
// Non-resizing write implementation
#[inline]
fn slice_write(pos_mut: &mut u64, slice: &mut [u8], buf: &[u8]) -> io::Result<usize> {
let pos = cmp::min(*pos_mut, slice.len() as u64);
let amt = (&mut slice[(pos as usize)..]).write(buf)?;
*pos_mut += amt as u64;
Ok(amt)
}
// Resizing write implementation
#[cfg(feature = "collections")]
fn vec_write(pos_mut: &mut u64, vec: &mut Vec<u8>, buf: &[u8]) -> io::Result<usize> {
let pos: usize = (*pos_mut).try_into().map_err(|_| {
Error::new(
ErrorKind::InvalidInput,
"cursor position exceeds maximum possible vector length",
)
})?;
// Make sure the internal buffer is as least as big as where we
// currently are
let len = vec.len();
if len < pos {
// use `resize` so that the zero filling is as efficient as possible
vec.resize(pos, 0);
}
// Figure out what bytes will be used to overwrite what's currently
// there (left), and what will be appended on the end (right)
{
let space = vec.len() - pos;
let (left, right) = buf.split_at(cmp::min(space, buf.len()));
vec[pos..pos + left.len()].copy_from_slice(left);
vec.extend_from_slice(right);
}
// Bump us forward
*pos_mut = (pos + buf.len()) as u64;
Ok(buf.len())
}
impl Write for Cursor<&mut [u8]> {
#[inline]
fn write(&mut self, buf: &[u8]) -> io::Result<usize> {
slice_write(&mut self.pos, self.inner, buf)
}
#[inline]
fn flush(&mut self) -> io::Result<()> {
Ok(())
}
}
#[cfg(feature = "collections")]
impl Write for Cursor<&mut Vec<u8>> {
fn write(&mut self, buf: &[u8]) -> io::Result<usize> {
vec_write(&mut self.pos, self.inner, buf)
}
#[inline]
fn flush(&mut self) -> io::Result<()> {
Ok(())
}
}
#[cfg(feature = "collections")]
impl Write for Cursor<Vec<u8>> {
fn write(&mut self, buf: &[u8]) -> io::Result<usize> {
vec_write(&mut self.pos, &mut self.inner, buf)
}
#[inline]
fn flush(&mut self) -> io::Result<()> {
Ok(())
}
}
#[cfg(feature = "alloc")]
impl Write for Cursor<Box<[u8]>> {
#[inline]
fn write(&mut self, buf: &[u8]) -> io::Result<usize> {
slice_write(&mut self.pos, &mut self.inner, buf)
}
#[inline]
fn flush(&mut self) -> io::Result<()> {
Ok(())
}
}
#[cfg(test)]
mod tests {
use crate::io::prelude::*;
use crate::io::{Cursor, IoSlice, IoSliceMut, SeekFrom};
#[test]
fn test_vec_writer() {
let mut writer = Vec::new();
assert_eq!(writer.write(&[0]).unwrap(), 1);
assert_eq!(writer.write(&[1, 2, 3]).unwrap(), 3);
assert_eq!(writer.write(&[4, 5, 6, 7]).unwrap(), 4);
assert_eq!(
writer
.write_vectored(&[IoSlice::new(&[]), IoSlice::new(&[8, 9]), IoSlice::new(&[10])],)
.unwrap(),
3
);
let b: &[_] = &[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10];
assert_eq!(writer, b);
}
#[test]
fn test_mem_writer() {
let mut writer = Cursor::new(Vec::new());
assert_eq!(writer.write(&[0]).unwrap(), 1);
assert_eq!(writer.write(&[1, 2, 3]).unwrap(), 3);
assert_eq!(writer.write(&[4, 5, 6, 7]).unwrap(), 4);
assert_eq!(
writer
.write_vectored(&[IoSlice::new(&[]), IoSlice::new(&[8, 9]), IoSlice::new(&[10])],)
.unwrap(),
3
);
let b: &[_] = &[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10];
assert_eq!(&writer.get_ref()[..], b);
}
#[test]
fn test_mem_mut_writer() {
let mut vec = Vec::new();
let mut writer = Cursor::new(&mut vec);
assert_eq!(writer.write(&[0]).unwrap(), 1);
assert_eq!(writer.write(&[1, 2, 3]).unwrap(), 3);
assert_eq!(writer.write(&[4, 5, 6, 7]).unwrap(), 4);
assert_eq!(
writer
.write_vectored(&[IoSlice::new(&[]), IoSlice::new(&[8, 9]), IoSlice::new(&[10])],)
.unwrap(),
3
);
let b: &[_] = &[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10];
assert_eq!(&writer.get_ref()[..], b);
}
#[test]
fn test_box_slice_writer() {
let mut writer = Cursor::new(vec![0u8; 9].into_boxed_slice());
assert_eq!(writer.position(), 0);
assert_eq!(writer.write(&[0]).unwrap(), 1);
assert_eq!(writer.position(), 1);
assert_eq!(writer.write(&[1, 2, 3]).unwrap(), 3);
assert_eq!(writer.write(&[4, 5, 6, 7]).unwrap(), 4);
assert_eq!(writer.position(), 8);
assert_eq!(writer.write(&[]).unwrap(), 0);
assert_eq!(writer.position(), 8);
assert_eq!(writer.write(&[8, 9]).unwrap(), 1);
assert_eq!(writer.write(&[10]).unwrap(), 0);
let b: &[_] = &[0, 1, 2, 3, 4, 5, 6, 7, 8];
assert_eq!(&**writer.get_ref(), b);
}
#[test]
fn test_box_slice_writer_vectored() {
let mut writer = Cursor::new(vec![0u8; 9].into_boxed_slice());
assert_eq!(writer.position(), 0);
assert_eq!(writer.write_vectored(&[IoSlice::new(&[0])]).unwrap(), 1);
assert_eq!(writer.position(), 1);
assert_eq!(
writer
.write_vectored(&[IoSlice::new(&[1, 2, 3]), IoSlice::new(&[4, 5, 6, 7]),])
.unwrap(),
7,
);
assert_eq!(writer.position(), 8);
assert_eq!(writer.write_vectored(&[]).unwrap(), 0);
assert_eq!(writer.position(), 8);
assert_eq!(writer.write_vectored(&[IoSlice::new(&[8, 9])]).unwrap(), 1);
assert_eq!(writer.write_vectored(&[IoSlice::new(&[10])]).unwrap(), 0);
let b: &[_] = &[0, 1, 2, 3, 4, 5, 6, 7, 8];
assert_eq!(&**writer.get_ref(), b);
}
#[test]
fn test_buf_writer() {
let mut buf = [0 as u8; 9];
{
let mut writer = Cursor::new(&mut buf[..]);
assert_eq!(writer.position(), 0);
assert_eq!(writer.write(&[0]).unwrap(), 1);
assert_eq!(writer.position(), 1);
assert_eq!(writer.write(&[1, 2, 3]).unwrap(), 3);
assert_eq!(writer.write(&[4, 5, 6, 7]).unwrap(), 4);
assert_eq!(writer.position(), 8);
assert_eq!(writer.write(&[]).unwrap(), 0);
assert_eq!(writer.position(), 8);
assert_eq!(writer.write(&[8, 9]).unwrap(), 1);
assert_eq!(writer.write(&[10]).unwrap(), 0);
}
let b: &[_] = &[0, 1, 2, 3, 4, 5, 6, 7, 8];
assert_eq!(buf, b);
}
#[test]
fn test_buf_writer_vectored() {
let mut buf = [0 as u8; 9];
{
let mut writer = Cursor::new(&mut buf[..]);
assert_eq!(writer.position(), 0);
assert_eq!(writer.write_vectored(&[IoSlice::new(&[0])]).unwrap(), 1);
assert_eq!(writer.position(), 1);
assert_eq!(
writer
.write_vectored(&[IoSlice::new(&[1, 2, 3]), IoSlice::new(&[4, 5, 6, 7])],)
.unwrap(),
7,
);
assert_eq!(writer.position(), 8);
assert_eq!(writer.write_vectored(&[]).unwrap(), 0);
assert_eq!(writer.position(), 8);
assert_eq!(writer.write_vectored(&[IoSlice::new(&[8, 9])]).unwrap(), 1);
assert_eq!(writer.write_vectored(&[IoSlice::new(&[10])]).unwrap(), 0);
}
let b: &[_] = &[0, 1, 2, 3, 4, 5, 6, 7, 8];
assert_eq!(buf, b);
}
#[test]
fn test_buf_writer_seek() {
let mut buf = [0 as u8; 8];
{
let mut writer = Cursor::new(&mut buf[..]);
assert_eq!(writer.position(), 0);
assert_eq!(writer.write(&[1]).unwrap(), 1);
assert_eq!(writer.position(), 1);
assert_eq!(writer.seek(SeekFrom::Start(2)).unwrap(), 2);
assert_eq!(writer.position(), 2);
assert_eq!(writer.write(&[2]).unwrap(), 1);
assert_eq!(writer.position(), 3);
assert_eq!(writer.seek(SeekFrom::Current(-2)).unwrap(), 1);
assert_eq!(writer.position(), 1);
assert_eq!(writer.write(&[3]).unwrap(), 1);
assert_eq!(writer.position(), 2);
assert_eq!(writer.seek(SeekFrom::End(-1)).unwrap(), 7);
assert_eq!(writer.position(), 7);
assert_eq!(writer.write(&[4]).unwrap(), 1);
assert_eq!(writer.position(), 8);
}
let b: &[_] = &[1, 3, 2, 0, 0, 0, 0, 4];
assert_eq!(buf, b);
}
#[test]
fn test_buf_writer_error() {
let mut buf = [0 as u8; 2];
let mut writer = Cursor::new(&mut buf[..]);
assert_eq!(writer.write(&[0]).unwrap(), 1);
assert_eq!(writer.write(&[0, 0]).unwrap(), 1);
assert_eq!(writer.write(&[0, 0]).unwrap(), 0);
}
#[test]
fn test_mem_reader() {
let mut reader = Cursor::new(vec![0, 1, 2, 3, 4, 5, 6, 7]);
let mut buf = [];
assert_eq!(reader.read(&mut buf).unwrap(), 0);
assert_eq!(reader.position(), 0);
let mut buf = [0];
assert_eq!(reader.read(&mut buf).unwrap(), 1);
assert_eq!(reader.position(), 1);
let b: &[_] = &[0];
assert_eq!(buf, b);
let mut buf = [0; 4];
assert_eq!(reader.read(&mut buf).unwrap(), 4);
assert_eq!(reader.position(), 5);
let b: &[_] = &[1, 2, 3, 4];
assert_eq!(buf, b);
assert_eq!(reader.read(&mut buf).unwrap(), 3);
let b: &[_] = &[5, 6, 7];
assert_eq!(&buf[..3], b);
assert_eq!(reader.read(&mut buf).unwrap(), 0);
}
#[test]
fn test_mem_reader_vectored() {
let mut reader = Cursor::new(vec![0, 1, 2, 3, 4, 5, 6, 7]);
let mut buf = [];
assert_eq!(reader.read_vectored(&mut [IoSliceMut::new(&mut buf)]).unwrap(), 0);
assert_eq!(reader.position(), 0);
let mut buf = [0];
assert_eq!(
reader
.read_vectored(&mut [IoSliceMut::new(&mut []), IoSliceMut::new(&mut buf),])
.unwrap(),
1,
);
assert_eq!(reader.position(), 1);
let b: &[_] = &[0];
assert_eq!(buf, b);
let mut buf1 = [0; 4];
let mut buf2 = [0; 4];
assert_eq!(
reader
.read_vectored(&mut [IoSliceMut::new(&mut buf1), IoSliceMut::new(&mut buf2),])
.unwrap(),
7,
);
let b1: &[_] = &[1, 2, 3, 4];
let b2: &[_] = &[5, 6, 7];
assert_eq!(buf1, b1);
assert_eq!(&buf2[..3], b2);
assert_eq!(reader.read(&mut buf).unwrap(), 0);
}
#[test]
fn test_boxed_slice_reader() {
let mut reader = Cursor::new(vec![0, 1, 2, 3, 4, 5, 6, 7].into_boxed_slice());
let mut buf = [];
assert_eq!(reader.read(&mut buf).unwrap(), 0);
assert_eq!(reader.position(), 0);
let mut buf = [0];
assert_eq!(reader.read(&mut buf).unwrap(), 1);
assert_eq!(reader.position(), 1);
let b: &[_] = &[0];
assert_eq!(buf, b);
let mut buf = [0; 4];
assert_eq!(reader.read(&mut buf).unwrap(), 4);
assert_eq!(reader.position(), 5);
let b: &[_] = &[1, 2, 3, 4];
assert_eq!(buf, b);
assert_eq!(reader.read(&mut buf).unwrap(), 3);
let b: &[_] = &[5, 6, 7];
assert_eq!(&buf[..3], b);
assert_eq!(reader.read(&mut buf).unwrap(), 0);
}
#[test]
fn test_boxed_slice_reader_vectored() {
let mut reader = Cursor::new(vec![0, 1, 2, 3, 4, 5, 6, 7].into_boxed_slice());
let mut buf = [];
assert_eq!(reader.read_vectored(&mut [IoSliceMut::new(&mut buf)]).unwrap(), 0);
assert_eq!(reader.position(), 0);
let mut buf = [0];
assert_eq!(
reader
.read_vectored(&mut [IoSliceMut::new(&mut []), IoSliceMut::new(&mut buf),])
.unwrap(),
1,
);
assert_eq!(reader.position(), 1);
let b: &[_] = &[0];
assert_eq!(buf, b);
let mut buf1 = [0; 4];
let mut buf2 = [0; 4];
assert_eq!(
reader
.read_vectored(&mut [IoSliceMut::new(&mut buf1), IoSliceMut::new(&mut buf2)],)
.unwrap(),
7,
);
let b1: &[_] = &[1, 2, 3, 4];
let b2: &[_] = &[5, 6, 7];
assert_eq!(buf1, b1);
assert_eq!(&buf2[..3], b2);
assert_eq!(reader.read(&mut buf).unwrap(), 0);
}
#[test]
fn read_to_end() {
let mut reader = Cursor::new(vec![0, 1, 2, 3, 4, 5, 6, 7]);
let mut v = Vec::new();
reader.read_to_end(&mut v).unwrap();
assert_eq!(v, [0, 1, 2, 3, 4, 5, 6, 7]);
}
#[test]
fn test_slice_reader() {
let in_buf = vec![0, 1, 2, 3, 4, 5, 6, 7];
let reader = &mut &in_buf[..];
let mut buf = [];
assert_eq!(reader.read(&mut buf).unwrap(), 0);
let mut buf = [0];
assert_eq!(reader.read(&mut buf).unwrap(), 1);
assert_eq!(reader.len(), 7);
let b: &[_] = &[0];
assert_eq!(&buf[..], b);
let mut buf = [0; 4];
assert_eq!(reader.read(&mut buf).unwrap(), 4);
assert_eq!(reader.len(), 3);
let b: &[_] = &[1, 2, 3, 4];
assert_eq!(&buf[..], b);
assert_eq!(reader.read(&mut buf).unwrap(), 3);
let b: &[_] = &[5, 6, 7];
assert_eq!(&buf[..3], b);
assert_eq!(reader.read(&mut buf).unwrap(), 0);
}
#[test]
fn test_slice_reader_vectored() {
let in_buf = vec![0, 1, 2, 3, 4, 5, 6, 7];
let reader = &mut &in_buf[..];
let mut buf = [];
assert_eq!(reader.read_vectored(&mut [IoSliceMut::new(&mut buf)]).unwrap(), 0);
let mut buf = [0];
assert_eq!(
reader
.read_vectored(&mut [IoSliceMut::new(&mut []), IoSliceMut::new(&mut buf),])
.unwrap(),
1,
);
assert_eq!(reader.len(), 7);
let b: &[_] = &[0];
assert_eq!(buf, b);
let mut buf1 = [0; 4];
let mut buf2 = [0; 4];
assert_eq!(
reader
.read_vectored(&mut [IoSliceMut::new(&mut buf1), IoSliceMut::new(&mut buf2)],)
.unwrap(),
7,
);
let b1: &[_] = &[1, 2, 3, 4];
let b2: &[_] = &[5, 6, 7];
assert_eq!(buf1, b1);
assert_eq!(&buf2[..3], b2);
assert_eq!(reader.read(&mut buf).unwrap(), 0);
}
#[test]
fn test_read_exact() {
let in_buf = vec![0, 1, 2, 3, 4, 5, 6, 7];
let reader = &mut &in_buf[..];
let mut buf = [];
assert!(reader.read_exact(&mut buf).is_ok());
let mut buf = [8];
assert!(reader.read_exact(&mut buf).is_ok());
assert_eq!(buf[0], 0);
assert_eq!(reader.len(), 7);
let mut buf = [0, 0, 0, 0, 0, 0, 0];
assert!(reader.read_exact(&mut buf).is_ok());
assert_eq!(buf, [1, 2, 3, 4, 5, 6, 7]);
assert_eq!(reader.len(), 0);
let mut buf = [0];
assert!(reader.read_exact(&mut buf).is_err());
}
#[test]
fn test_buf_reader() {
let in_buf = vec![0, 1, 2, 3, 4, 5, 6, 7];
let mut reader = Cursor::new(&in_buf[..]);
let mut buf = [];
assert_eq!(reader.read(&mut buf).unwrap(), 0);
assert_eq!(reader.position(), 0);
let mut buf = [0];
assert_eq!(reader.read(&mut buf).unwrap(), 1);
assert_eq!(reader.position(), 1);
let b: &[_] = &[0];
assert_eq!(buf, b);
let mut buf = [0; 4];
assert_eq!(reader.read(&mut buf).unwrap(), 4);
assert_eq!(reader.position(), 5);
let b: &[_] = &[1, 2, 3, 4];
assert_eq!(buf, b);
assert_eq!(reader.read(&mut buf).unwrap(), 3);
let b: &[_] = &[5, 6, 7];
assert_eq!(&buf[..3], b);
assert_eq!(reader.read(&mut buf).unwrap(), 0);
}
#[test]
fn seek_past_end() {
let buf = [0xff];
let mut r = Cursor::new(&buf[..]);
assert_eq!(r.seek(SeekFrom::Start(10)).unwrap(), 10);
assert_eq!(r.read(&mut [0]).unwrap(), 0);
let mut r = Cursor::new(vec![10]);
assert_eq!(r.seek(SeekFrom::Start(10)).unwrap(), 10);
assert_eq!(r.read(&mut [0]).unwrap(), 0);
let mut buf = [0];
let mut r = Cursor::new(&mut buf[..]);
assert_eq!(r.seek(SeekFrom::Start(10)).unwrap(), 10);
assert_eq!(r.write(&[3]).unwrap(), 0);
let mut r = Cursor::new(vec![10].into_boxed_slice());
assert_eq!(r.seek(SeekFrom::Start(10)).unwrap(), 10);
assert_eq!(r.write(&[3]).unwrap(), 0);
}
#[test]
fn seek_past_i64() {
let buf = [0xff];
let mut r = Cursor::new(&buf[..]);
assert_eq!(r.seek(SeekFrom::Start(6)).unwrap(), 6);
assert_eq!(r.seek(SeekFrom::Current(0x7ffffffffffffff0)).unwrap(), 0x7ffffffffffffff6);
assert_eq!(r.seek(SeekFrom::Current(0x10)).unwrap(), 0x8000000000000006);
assert_eq!(r.seek(SeekFrom::Current(0)).unwrap(), 0x8000000000000006);
assert!(r.seek(SeekFrom::Current(0x7ffffffffffffffd)).is_err());
assert_eq!(r.seek(SeekFrom::Current(-0x8000000000000000)).unwrap(), 6);
let mut r = Cursor::new(vec![10]);
assert_eq!(r.seek(SeekFrom::Start(6)).unwrap(), 6);
assert_eq!(r.seek(SeekFrom::Current(0x7ffffffffffffff0)).unwrap(), 0x7ffffffffffffff6);
assert_eq!(r.seek(SeekFrom::Current(0x10)).unwrap(), 0x8000000000000006);
assert_eq!(r.seek(SeekFrom::Current(0)).unwrap(), 0x8000000000000006);
assert!(r.seek(SeekFrom::Current(0x7ffffffffffffffd)).is_err());
assert_eq!(r.seek(SeekFrom::Current(-0x8000000000000000)).unwrap(), 6);
let mut buf = [0];
let mut r = Cursor::new(&mut buf[..]);
assert_eq!(r.seek(SeekFrom::Start(6)).unwrap(), 6);
assert_eq!(r.seek(SeekFrom::Current(0x7ffffffffffffff0)).unwrap(), 0x7ffffffffffffff6);
assert_eq!(r.seek(SeekFrom::Current(0x10)).unwrap(), 0x8000000000000006);
assert_eq!(r.seek(SeekFrom::Current(0)).unwrap(), 0x8000000000000006);
assert!(r.seek(SeekFrom::Current(0x7ffffffffffffffd)).is_err());
assert_eq!(r.seek(SeekFrom::Current(-0x8000000000000000)).unwrap(), 6);
let mut r = Cursor::new(vec![10].into_boxed_slice());
assert_eq!(r.seek(SeekFrom::Start(6)).unwrap(), 6);
assert_eq!(r.seek(SeekFrom::Current(0x7ffffffffffffff0)).unwrap(), 0x7ffffffffffffff6);
assert_eq!(r.seek(SeekFrom::Current(0x10)).unwrap(), 0x8000000000000006);
assert_eq!(r.seek(SeekFrom::Current(0)).unwrap(), 0x8000000000000006);
assert!(r.seek(SeekFrom::Current(0x7ffffffffffffffd)).is_err());
assert_eq!(r.seek(SeekFrom::Current(-0x8000000000000000)).unwrap(), 6);
}
#[test]
fn seek_before_0() {
let buf = [0xff];
let mut r = Cursor::new(&buf[..]);
assert!(r.seek(SeekFrom::End(-2)).is_err());
let mut r = Cursor::new(vec![10]);
assert!(r.seek(SeekFrom::End(-2)).is_err());
let mut buf = [0];
let mut r = Cursor::new(&mut buf[..]);
assert!(r.seek(SeekFrom::End(-2)).is_err());
let mut r = Cursor::new(vec![10].into_boxed_slice());
assert!(r.seek(SeekFrom::End(-2)).is_err());
}
#[test]
fn test_seekable_mem_writer() {
let mut writer = Cursor::new(Vec::<u8>::new());
assert_eq!(writer.position(), 0);
assert_eq!(writer.write(&[0]).unwrap(), 1);
assert_eq!(writer.position(), 1);
assert_eq!(writer.write(&[1, 2, 3]).unwrap(), 3);
assert_eq!(writer.write(&[4, 5, 6, 7]).unwrap(), 4);
assert_eq!(writer.position(), 8);
let b: &[_] = &[0, 1, 2, 3, 4, 5, 6, 7];
assert_eq!(&writer.get_ref()[..], b);
assert_eq!(writer.seek(SeekFrom::Start(0)).unwrap(), 0);
assert_eq!(writer.position(), 0);
assert_eq!(writer.write(&[3, 4]).unwrap(), 2);
let b: &[_] = &[3, 4, 2, 3, 4, 5, 6, 7];
assert_eq!(&writer.get_ref()[..], b);
assert_eq!(writer.seek(SeekFrom::Current(1)).unwrap(), 3);
assert_eq!(writer.write(&[0, 1]).unwrap(), 2);
let b: &[_] = &[3, 4, 2, 0, 1, 5, 6, 7];
assert_eq!(&writer.get_ref()[..], b);
assert_eq!(writer.seek(SeekFrom::End(-1)).unwrap(), 7);
assert_eq!(writer.write(&[1, 2]).unwrap(), 2);
let b: &[_] = &[3, 4, 2, 0, 1, 5, 6, 1, 2];
assert_eq!(&writer.get_ref()[..], b);
assert_eq!(writer.seek(SeekFrom::End(1)).unwrap(), 10);
assert_eq!(writer.write(&[1]).unwrap(), 1);
let b: &[_] = &[3, 4, 2, 0, 1, 5, 6, 1, 2, 0, 1];
assert_eq!(&writer.get_ref()[..], b);
}
#[test]
fn vec_seek_past_end() {
let mut r = Cursor::new(Vec::new());
assert_eq!(r.seek(SeekFrom::Start(10)).unwrap(), 10);
assert_eq!(r.write(&[3]).unwrap(), 1);
}
#[test]
fn vec_seek_before_0() {
let mut r = Cursor::new(Vec::new());
assert!(r.seek(SeekFrom::End(-2)).is_err());
}
#[test]
#[cfg(target_pointer_width = "32")]
fn vec_seek_and_write_past_usize_max() {
let mut c = Cursor::new(Vec::new());
c.set_position(<usize>::max_value() as u64 + 1);
assert!(c.write_all(&[1, 2, 3]).is_err());
}
#[test]
fn test_partial_eq() {
assert_eq!(Cursor::new(Vec::<u8>::new()), Cursor::new(Vec::<u8>::new()));
}
#[test]
fn test_eq() {
struct AssertEq<T: Eq>(pub T);
let _: AssertEq<Cursor<Vec<u8>>> = AssertEq(Cursor::new(Vec::new()));
}
}

551
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@ -0,0 +1,551 @@
#[cfg(feature="alloc")] use alloc::boxed::Box;
#[cfg(not(feature="alloc"))] use ::FakeBox as Box;
use core::convert::Into;
use core::fmt;
use core::marker::{Send, Sync};
use core::option::Option::{self, Some, None};
use core::result;
#[cfg(feature="collections")] use collections::string::String;
#[cfg(not(feature="collections"))] use ::ErrorString as String;
use core::convert::From;
/// A specialized [`Result`](../result/enum.Result.html) type for I/O
/// operations.
///
/// This type is broadly used across [`std::io`] for any operation which may
/// produce an error.
///
/// This typedef is generally used to avoid writing out [`io::Error`] directly and
/// is otherwise a direct mapping to [`Result`].
///
/// While usual Rust style is to import types directly, aliases of [`Result`]
/// often are not, to make it easier to distinguish between them. [`Result`] is
/// generally assumed to be [`std::result::Result`][`Result`], and so users of this alias
/// will generally use `io::Result` instead of shadowing the prelude's import
/// of [`std::result::Result`][`Result`].
///
/// [`std::io`]: ../io/index.html
/// [`io::Error`]: ../io/struct.Error.html
/// [`Result`]: ../result/enum.Result.html
///
/// # Examples
///
/// A convenience function that bubbles an `io::Result` to its caller:
///
/// ```
/// use std::io;
///
/// fn get_string() -> io::Result<String> {
/// let mut buffer = String::new();
///
/// io::stdin().read_line(&mut buffer)?;
///
/// Ok(buffer)
/// }
/// ```
pub type Result<T> = result::Result<T, Error>;
/// The error type for I/O operations of the [`Read`], [`Write`], [`Seek`], and
/// associated traits.
///
/// Errors mostly originate from the underlying OS, but custom instances of
/// `Error` can be created with crafted error messages and a particular value of
/// [`ErrorKind`].
///
/// [`Read`]: ../io/trait.Read.html
/// [`Write`]: ../io/trait.Write.html
/// [`Seek`]: ../io/trait.Seek.html
/// [`ErrorKind`]: enum.ErrorKind.html
pub struct Error {
repr: Repr,
}
impl fmt::Debug for Error {
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
fmt::Debug::fmt(&self.repr, f)
}
}
enum Repr {
Os(i32),
Simple(ErrorKind),
#[cfg(feature="alloc")]
Custom(Box<Custom>),
#[cfg(not(feature="alloc"))]
Custom(Custom),
}
#[derive(Debug)]
struct Custom {
kind: ErrorKind,
error: String,
}
/// A list specifying general categories of I/O error.
///
/// This list is intended to grow over time and it is not recommended to
/// exhaustively match against it.
///
/// It is used with the [`io::Error`] type.
///
/// [`io::Error`]: struct.Error.html
#[derive(Clone, Copy, Debug, Eq, Hash, Ord, PartialEq, PartialOrd)]
#[allow(deprecated)]
#[non_exhaustive]
pub enum ErrorKind {
/// An entity was not found, often a file.
NotFound,
/// The operation lacked the necessary privileges to complete.
PermissionDenied,
/// The connection was refused by the remote server.
ConnectionRefused,
/// The connection was reset by the remote server.
ConnectionReset,
/// The connection was aborted (terminated) by the remote server.
ConnectionAborted,
/// The network operation failed because it was not connected yet.
NotConnected,
/// A socket address could not be bound because the address is already in
/// use elsewhere.
AddrInUse,
/// A nonexistent interface was requested or the requested address was not
/// local.
AddrNotAvailable,
/// The operation failed because a pipe was closed.
BrokenPipe,
/// An entity already exists, often a file.
AlreadyExists,
/// The operation needs to block to complete, but the blocking operation was
/// requested to not occur.
WouldBlock,
/// A parameter was incorrect.
InvalidInput,
/// Data not valid for the operation were encountered.
///
/// Unlike [`InvalidInput`], this typically means that the operation
/// parameters were valid, however the error was caused by malformed
/// input data.
///
/// For example, a function that reads a file into a string will error with
/// `InvalidData` if the file's contents are not valid UTF-8.
///
/// [`InvalidInput`]: #variant.InvalidInput
InvalidData,
/// The I/O operation's timeout expired, causing it to be canceled.
TimedOut,
/// An error returned when an operation could not be completed because a
/// call to [`write`] returned [`Ok(0)`].
///
/// This typically means that an operation could only succeed if it wrote a
/// particular number of bytes but only a smaller number of bytes could be
/// written.
///
/// [`write`]: ../../std/io/trait.Write.html#tymethod.write
/// [`Ok(0)`]: ../../std/io/type.Result.html
WriteZero,
/// This operation was interrupted.
///
/// Interrupted operations can typically be retried.
Interrupted,
/// Any I/O error not part of this list.
Other,
/// An error returned when an operation could not be completed because an
/// "end of file" was reached prematurely.
///
/// This typically means that an operation could only succeed if it read a
/// particular number of bytes but only a smaller number of bytes could be
/// read.
UnexpectedEof,
}
impl ErrorKind {
pub(crate) fn as_str(&self) -> &'static str {
match *self {
ErrorKind::NotFound => "entity not found",
ErrorKind::PermissionDenied => "permission denied",
ErrorKind::ConnectionRefused => "connection refused",
ErrorKind::ConnectionReset => "connection reset",
ErrorKind::ConnectionAborted => "connection aborted",
ErrorKind::NotConnected => "not connected",
ErrorKind::AddrInUse => "address in use",
ErrorKind::AddrNotAvailable => "address not available",
ErrorKind::BrokenPipe => "broken pipe",
ErrorKind::AlreadyExists => "entity already exists",
ErrorKind::WouldBlock => "operation would block",
ErrorKind::InvalidInput => "invalid input parameter",
ErrorKind::InvalidData => "invalid data",
ErrorKind::TimedOut => "timed out",
ErrorKind::WriteZero => "write zero",
ErrorKind::Interrupted => "operation interrupted",
ErrorKind::Other => "other os error",
ErrorKind::UnexpectedEof => "unexpected end of file",
}
}
}
/// Intended for use for errors not exposed to the user, where allocating onto
/// the heap (for normal construction via Error::new) is too costly.
impl From<ErrorKind> for Error {
/// Converts an [`ErrorKind`] into an [`Error`].
///
/// This conversion allocates a new error with a simple representation of error kind.
///
/// # Examples
///
/// ```
/// use std::io::{Error, ErrorKind};
///
/// let not_found = ErrorKind::NotFound;
/// let error = Error::from(not_found);
/// assert_eq!("entity not found", format!("{}", error));
/// ```
///
/// [`ErrorKind`]: ../../std/io/enum.ErrorKind.html
/// [`Error`]: ../../std/io/struct.Error.html
#[inline]
fn from(kind: ErrorKind) -> Error {
Error { repr: Repr::Simple(kind) }
}
}
impl Error {
/// Creates a new I/O error from a known kind of error as well as an
/// arbitrary error payload.
///
/// This function is used to generically create I/O errors which do not
/// originate from the OS itself. The `error` argument is an arbitrary
/// payload which will be contained in this `Error`.
///
/// # Examples
///
/// ```
/// use std::io::{Error, ErrorKind};
///
/// // errors can be created from strings
/// let custom_error = Error::new(ErrorKind::Other, "oh no!");
///
/// // errors can also be created from other errors
/// let custom_error2 = Error::new(ErrorKind::Interrupted, custom_error);
/// ```
pub fn new<E>(kind: ErrorKind, error: E) -> Error
where
E: Into<String>,
{
Self::_new(kind, error.into())
}
fn _new(kind: ErrorKind, error: String) -> Error {
Error { repr: Repr::Custom(Box::new(Custom { kind, error })) }
}
/// Creates a new instance of an `Error` from a particular OS error code.
///
/// # Examples
///
/// On Linux:
///
/// ```
/// # if cfg!(target_os = "linux") {
/// use std::io;
///
/// let error = io::Error::from_raw_os_error(22);
/// assert_eq!(error.kind(), io::ErrorKind::InvalidInput);
/// # }
/// ```
///
/// On Windows:
///
/// ```
/// # if cfg!(windows) {
/// use std::io;
///
/// let error = io::Error::from_raw_os_error(10022);
/// assert_eq!(error.kind(), io::ErrorKind::InvalidInput);
/// # }
/// ```
pub fn from_raw_os_error(code: i32) -> Error {
Error { repr: Repr::Os(code) }
}
/// Returns the OS error that this error represents (if any).
///
/// If this `Error` was constructed via `last_os_error` or
/// `from_raw_os_error`, then this function will return `Some`, otherwise
/// it will return `None`.
///
/// # Examples
///
/// ```
/// use std::io::{Error, ErrorKind};
///
/// fn print_os_error(err: &Error) {
/// if let Some(raw_os_err) = err.raw_os_error() {
/// println!("raw OS error: {:?}", raw_os_err);
/// } else {
/// println!("Not an OS error");
/// }
/// }
///
/// fn main() {
/// // Will print "raw OS error: ...".
/// print_os_error(&Error::last_os_error());
/// // Will print "Not an OS error".
/// print_os_error(&Error::new(ErrorKind::Other, "oh no!"));
/// }
/// ```
pub fn raw_os_error(&self) -> Option<i32> {
match self.repr {
Repr::Os(i) => Some(i),
Repr::Custom(..) => None,
Repr::Simple(..) => None,
}
}
/// Returns a reference to the inner error wrapped by this error (if any).
///
/// If this `Error` was constructed via `new` then this function will
/// return `Some`, otherwise it will return `None`.
///
/// # Examples
///
/// ```
/// use std::io::{Error, ErrorKind};
///
/// fn print_error(err: &Error) {
/// if let Some(inner_err) = err.get_ref() {
/// println!("Inner error: {:?}", inner_err);
/// } else {
/// println!("No inner error");
/// }
/// }
///
/// fn main() {
/// // Will print "No inner error".
/// print_error(&Error::last_os_error());
/// // Will print "Inner error: ...".
/// print_error(&Error::new(ErrorKind::Other, "oh no!"));
/// }
/// ```
pub fn get_ref(&self) -> Option<&String> {
match self.repr {
Repr::Os(..) => None,
Repr::Simple(..) => None,
Repr::Custom(ref c) => Some(&c.error),
}
}
/// Returns a mutable reference to the inner error wrapped by this error
/// (if any).
///
/// If this `Error` was constructed via `new` then this function will
/// return `Some`, otherwise it will return `None`.
///
/// # Examples
///
/// ```
/// use std::io::{Error, ErrorKind};
/// use std::{error, fmt};
/// use std::fmt::Display;
///
/// #[derive(Debug)]
/// struct MyError {
/// v: String,
/// }
///
/// impl MyError {
/// fn new() -> MyError {
/// MyError {
/// v: "oh no!".to_string()
/// }
/// }
///
/// fn change_message(&mut self, new_message: &str) {
/// self.v = new_message.to_string();
/// }
/// }
///
/// impl error::Error for MyError {}
///
/// impl Display for MyError {
/// fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
/// write!(f, "MyError: {}", &self.v)
/// }
/// }
///
/// fn change_error(mut err: Error) -> Error {
/// if let Some(inner_err) = err.get_mut() {
/// inner_err.downcast_mut::<MyError>().unwrap().change_message("I've been changed!");
/// }
/// err
/// }
///
/// fn print_error(err: &Error) {
/// if let Some(inner_err) = err.get_ref() {
/// println!("Inner error: {}", inner_err);
/// } else {
/// println!("No inner error");
/// }
/// }
///
/// fn main() {
/// // Will print "No inner error".
/// print_error(&change_error(Error::last_os_error()));
/// // Will print "Inner error: ...".
/// print_error(&change_error(Error::new(ErrorKind::Other, MyError::new())));
/// }
/// ```
pub fn get_mut(&mut self) -> Option<&mut String> {
match self.repr {
Repr::Os(..) => None,
Repr::Simple(..) => None,
Repr::Custom(ref mut c) => Some(&mut c.error),
}
}
/// Consumes the `Error`, returning its inner error (if any).
///
/// If this `Error` was constructed via `new` then this function will
/// return `Some`, otherwise it will return `None`.
///
/// # Examples
///
/// ```
/// use std::io::{Error, ErrorKind};
///
/// fn print_error(err: Error) {
/// if let Some(inner_err) = err.into_inner() {
/// println!("Inner error: {}", inner_err);
/// } else {
/// println!("No inner error");
/// }
/// }
///
/// fn main() {
/// // Will print "No inner error".
/// print_error(Error::last_os_error());
/// // Will print "Inner error: ...".
/// print_error(Error::new(ErrorKind::Other, "oh no!"));
/// }
/// ```
pub fn into_inner(self) -> Option<String> {
match self.repr {
Repr::Os(..) => None,
Repr::Simple(..) => None,
Repr::Custom(c) => Some(c.error),
}
}
/// Returns the corresponding `ErrorKind` for this error.
///
/// # Examples
///
/// ```
/// use std::io::{Error, ErrorKind};
///
/// fn print_error(err: Error) {
/// println!("{:?}", err.kind());
/// }
///
/// fn main() {
/// // Will print "No inner error".
/// print_error(Error::last_os_error());
/// // Will print "Inner error: ...".
/// print_error(Error::new(ErrorKind::AddrInUse, "oh no!"));
/// }
/// ```
pub fn kind(&self) -> ErrorKind {
match self.repr {
Repr::Os(_code) => ErrorKind::Other,
Repr::Custom(ref c) => c.kind,
Repr::Simple(kind) => kind,
}
}
}
impl fmt::Debug for Repr {
fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
match *self {
Repr::Os(code) => fmt
.debug_struct("Os")
.field("code", &code)
.finish(),
Repr::Custom(ref c) => fmt::Debug::fmt(&c, fmt),
Repr::Simple(kind) => fmt.debug_tuple("Kind").field(&kind).finish(),
}
}
}
impl fmt::Display for Error {
fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result {
match self.repr {
Repr::Os(code) => {
write!(fmt, "os error {}", code)
}
Repr::Custom(ref c) => c.error.fmt(fmt),
Repr::Simple(kind) => write!(fmt, "{}", kind.as_str()),
}
}
}
fn _assert_error_is_sync_send() {
fn _is_sync_send<T: Sync + Send>() {}
_is_sync_send::<Error>();
}
#[cfg(test)]
mod test {
use super::{Custom, Error, ErrorKind, Repr};
use crate::error;
use crate::fmt;
use crate::sys::decode_error_kind;
use crate::sys::os::error_string;
#[test]
fn test_debug_error() {
let code = 6;
let msg = error_string(code);
let kind = decode_error_kind(code);
let err = Error {
repr: Repr::Custom(box Custom {
kind: ErrorKind::InvalidInput,
error: box Error { repr: super::Repr::Os(code) },
}),
};
let expected = format!(
"Custom {{ \
kind: InvalidInput, \
error: Os {{ \
code: {:?}, \
kind: {:?}, \
message: {:?} \
}} \
}}",
code, kind, msg
);
assert_eq!(format!("{:?}", err), expected);
}
#[test]
fn test_downcasting() {
#[derive(Debug)]
struct TestError;
impl fmt::Display for TestError {
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
f.write_str("asdf")
}
}
impl error::Error for TestError {}
// we have to call all of these UFCS style right now since method
// resolution won't implicitly drop the Send+Sync bounds
let mut err = Error::new(ErrorKind::Other, TestError);
assert!(err.get_ref().unwrap().is::<TestError>());
assert_eq!("asdf", err.get_ref().unwrap().to_string());
assert!(err.get_mut().unwrap().is::<TestError>());
let extracted = err.into_inner().unwrap();
extracted.downcast::<TestError>().unwrap();
}
}

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use core::cmp;
use core::fmt;
use crate::io::{
self, Error, ErrorKind, Initializer, Read, Seek, SeekFrom, Write,
};
#[cfg(feature = "collections")] use crate::io::BufRead;
use core::mem;
#[cfg(feature="collections")]
use collections::{
vec::Vec,
string::String,
};
#[cfg(feature = "alloc")]
use alloc::boxed::Box;
// =============================================================================
// Forwarding implementations
impl<R: Read + ?Sized> Read for &mut R {
#[inline]
fn read(&mut self, buf: &mut [u8]) -> io::Result<usize> {
(**self).read(buf)
}
#[inline]
unsafe fn initializer(&self) -> Initializer {
(**self).initializer()
}
#[cfg(feature="collections")]
#[inline]
fn read_to_end(&mut self, buf: &mut Vec<u8>) -> io::Result<usize> {
(**self).read_to_end(buf)
}
#[cfg(feature="collections")]
#[inline]
fn read_to_string(&mut self, buf: &mut String) -> io::Result<usize> {
(**self).read_to_string(buf)
}
#[inline]
fn read_exact(&mut self, buf: &mut [u8]) -> io::Result<()> {
(**self).read_exact(buf)
}
}
impl<W: Write + ?Sized> Write for &mut W {
#[inline]
fn write(&mut self, buf: &[u8]) -> io::Result<usize> {
(**self).write(buf)
}
#[inline]
fn flush(&mut self) -> io::Result<()> {
(**self).flush()
}
#[inline]
fn write_all(&mut self, buf: &[u8]) -> io::Result<()> {
(**self).write_all(buf)
}
#[inline]
fn write_fmt(&mut self, fmt: fmt::Arguments<'_>) -> io::Result<()> {
(**self).write_fmt(fmt)
}
}
impl<S: Seek + ?Sized> Seek for &mut S {
#[inline]
fn seek(&mut self, pos: SeekFrom) -> io::Result<u64> {
(**self).seek(pos)
}
}
#[cfg(feature = "collections")]
impl<B: BufRead + ?Sized> BufRead for &mut B {
#[inline]
fn fill_buf(&mut self) -> io::Result<&[u8]> {
(**self).fill_buf()
}
#[inline]
fn consume(&mut self, amt: usize) {
(**self).consume(amt)
}
#[cfg(feature="collections")]
#[inline]
fn read_until(&mut self, byte: u8, buf: &mut Vec<u8>) -> io::Result<usize> {
(**self).read_until(byte, buf)
}
#[cfg(feature="collections")]
#[inline]
fn read_line(&mut self, buf: &mut String) -> io::Result<usize> {
(**self).read_line(buf)
}
}
#[cfg(feature="alloc")]
#[cfg(feature="collections")]
impl<R: Read + ?Sized> Read for Box<R> {
#[inline]
fn read(&mut self, buf: &mut [u8]) -> io::Result<usize> {
(**self).read(buf)
}
#[cfg(feature="collections")]
#[inline]
fn read_to_end(&mut self, buf: &mut Vec<u8>) -> io::Result<usize> {
(**self).read_to_end(buf)
}
#[cfg(feature="collections")]
#[inline]
fn read_to_string(&mut self, buf: &mut String) -> io::Result<usize> {
(**self).read_to_string(buf)
}
#[inline]
fn read_exact(&mut self, buf: &mut [u8]) -> io::Result<()> {
(**self).read_exact(buf)
}
}
#[cfg(feature="alloc")]
#[cfg(feature="collections")]
impl<W: Write + ?Sized> Write for Box<W> {
#[inline]
fn write(&mut self, buf: &[u8]) -> io::Result<usize> {
(**self).write(buf)
}
#[inline]
fn flush(&mut self) -> io::Result<()> {
(**self).flush()
}
#[inline]
fn write_all(&mut self, buf: &[u8]) -> io::Result<()> {
(**self).write_all(buf)
}
#[inline]
fn write_fmt(&mut self, fmt: fmt::Arguments<'_>) -> io::Result<()> {
(**self).write_fmt(fmt)
}
}
#[cfg(feature="collections")]
impl<S: Seek + ?Sized> Seek for Box<S> {
#[inline]
fn seek(&mut self, pos: SeekFrom) -> io::Result<u64> {
(**self).seek(pos)
}
}
#[cfg(feature="collections")]
impl<B: BufRead + ?Sized> BufRead for Box<B> {
#[inline]
fn fill_buf(&mut self) -> io::Result<&[u8]> {
(**self).fill_buf()
}
#[inline]
fn consume(&mut self, amt: usize) {
(**self).consume(amt)
}
#[inline]
fn read_until(&mut self, byte: u8, buf: &mut Vec<u8>) -> io::Result<usize> {
(**self).read_until(byte, buf)
}
#[inline]
fn read_line(&mut self, buf: &mut String) -> io::Result<usize> {
(**self).read_line(buf)
}
}
// Used by panicking::default_hook
#[cfg(test)]
/// This impl is only used by printing logic, so any error returned is always
/// of kind `Other`, and should be ignored.
#[cfg(feature="collections")]
impl Write for Box<dyn (::realstd::io::Write) + Send> {
fn write(&mut self, buf: &[u8]) -> io::Result<usize> {
(**self).write(buf).map_err(|_| ErrorKind::Other.into())
}
fn flush(&mut self) -> io::Result<()> {
(**self).flush().map_err(|_| ErrorKind::Other.into())
}
}
// =============================================================================
// In-memory buffer implementations
/// Read is implemented for `&[u8]` by copying from the slice.
///
/// Note that reading updates the slice to point to the yet unread part.
/// The slice will be empty when EOF is reached.
impl Read for &[u8] {
#[inline]
fn read(&mut self, buf: &mut [u8]) -> io::Result<usize> {
let amt = cmp::min(buf.len(), self.len());
let (a, b) = self.split_at(amt);
// First check if the amount of bytes we want to read is small:
// `copy_from_slice` will generally expand to a call to `memcpy`, and
// for a single byte the overhead is significant.
if amt == 1 {
buf[0] = a[0];
} else {
buf[..amt].copy_from_slice(a);
}
*self = b;
Ok(amt)
}
#[inline]
unsafe fn initializer(&self) -> Initializer {
Initializer::nop()
}
#[inline]
fn read_exact(&mut self, buf: &mut [u8]) -> io::Result<()> {
if buf.len() > self.len() {
return Err(Error::new(ErrorKind::UnexpectedEof, "failed to fill whole buffer"));
}
let (a, b) = self.split_at(buf.len());
// First check if the amount of bytes we want to read is small:
// `copy_from_slice` will generally expand to a call to `memcpy`, and
// for a single byte the overhead is significant.
if buf.len() == 1 {
buf[0] = a[0];
} else {
buf.copy_from_slice(a);
}
*self = b;
Ok(())
}
#[cfg(feature="collections")]
#[inline]
fn read_to_end(&mut self, buf: &mut Vec<u8>) -> io::Result<usize> {
buf.extend_from_slice(*self);
let len = self.len();
*self = &self[len..];
Ok(len)
}
}
#[cfg(feature="collections")]
impl BufRead for &[u8] {
#[inline]
fn fill_buf(&mut self) -> io::Result<&[u8]> {
Ok(*self)
}
#[inline]
fn consume(&mut self, amt: usize) {
*self = &self[amt..];
}
}
/// Write is implemented for `&mut [u8]` by copying into the slice, overwriting
/// its data.
///
/// Note that writing updates the slice to point to the yet unwritten part.
/// The slice will be empty when it has been completely overwritten.
impl Write for &mut [u8] {
#[inline]
fn write(&mut self, data: &[u8]) -> io::Result<usize> {
let amt = cmp::min(data.len(), self.len());
let (a, b) = mem::replace(self, &mut []).split_at_mut(amt);
a.copy_from_slice(&data[..amt]);
*self = b;
Ok(amt)
}
#[inline]
fn write_all(&mut self, data: &[u8]) -> io::Result<()> {
if self.write(data)? == data.len() {
Ok(())
} else {
Err(Error::new(ErrorKind::WriteZero, "failed to write whole buffer"))
}
}
#[inline]
fn flush(&mut self) -> io::Result<()> {
Ok(())
}
}
/// Write is implemented for `Vec<u8>` by appending to the vector.
/// The vector will grow as needed.
#[cfg(feature="collections")]
impl Write for Vec<u8> {
#[inline]
fn write(&mut self, buf: &[u8]) -> io::Result<usize> {
self.extend_from_slice(buf);
Ok(buf.len())
}
#[inline]
fn write_all(&mut self, buf: &[u8]) -> io::Result<()> {
self.extend_from_slice(buf);
Ok(())
}
#[inline]
fn flush(&mut self) -> io::Result<()> {
Ok(())
}
}
#[cfg(test)]
mod tests {
use crate::io::prelude::*;
#[bench]
fn bench_read_slice(b: &mut test::Bencher) {
let buf = [5; 1024];
let mut dst = [0; 128];
b.iter(|| {
let mut rd = &buf[..];
for _ in 0..8 {
let _ = rd.read(&mut dst);
test::black_box(&dst);
}
})
}
#[bench]
fn bench_write_slice(b: &mut test::Bencher) {
let mut buf = [0; 1024];
let src = [5; 128];
b.iter(|| {
let mut wr = &mut buf[..];
for _ in 0..8 {
let _ = wr.write_all(&src);
test::black_box(&wr);
}
})
}
#[bench]
fn bench_read_vec(b: &mut test::Bencher) {
let buf = vec![5; 1024];
let mut dst = [0; 128];
b.iter(|| {
let mut rd = &buf[..];
for _ in 0..8 {
let _ = rd.read(&mut dst);
test::black_box(&dst);
}
})
}
#[bench]
fn bench_write_vec(b: &mut test::Bencher) {
let mut buf = Vec::with_capacity(1024);
let src = [5; 128];
b.iter(|| {
let mut wr = &mut buf[..];
for _ in 0..8 {
let _ = wr.write_all(&src);
test::black_box(&wr);
}
})
}
}

2664
src/libcoreio/src/io/mod.rs Normal file
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13
src/libcoreio/src/io/prelude.rs Normal file
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@ -0,0 +1,13 @@
//! The I/O Prelude
//!
//! The purpose of this module is to alleviate imports of many common I/O traits
//! by adding a glob import to the top of I/O heavy modules:
//!
//! ```
//! # #![allow(unused_imports)]
//! use std::io::prelude::*;
//! ```
pub use super::{Read, Seek, Write};
#[cfg(feature = "collections")] pub use super::BufRead;

269
src/libcoreio/src/io/util.rs Normal file
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@ -0,0 +1,269 @@
#![allow(missing_copy_implementations)]
use core::fmt;
use core::mem;
use crate::io::{self, ErrorKind, Initializer, Read, Write};
#[cfg(feature = "collections")] use crate::io::BufRead;
/// Copies the entire contents of a reader into a writer.
///
/// This function will continuously read data from `reader` and then
/// write it into `writer` in a streaming fashion until `reader`
/// returns EOF.
///
/// On success, the total number of bytes that were copied from
/// `reader` to `writer` is returned.
///
/// If you’re wanting to copy the contents of one file to another and you’re
/// working with filesystem paths, see the [`fs::copy`] function.
///
/// [`fs::copy`]: ../fs/fn.copy.html
///
/// # Errors
///
/// This function will return an error immediately if any call to `read` or
/// `write` returns an error. All instances of `ErrorKind::Interrupted` are
/// handled by this function and the underlying operation is retried.
///
/// # Examples
///
/// ```
/// use std::io;
///
/// fn main() -> io::Result<()> {
/// let mut reader: &[u8] = b"hello";
/// let mut writer: Vec<u8> = vec![];
///
/// io::copy(&mut reader, &mut writer)?;
///
/// assert_eq!(&b"hello"[..], &writer[..]);
/// Ok(())
/// }
/// ```
pub fn copy<R: ?Sized, W: ?Sized>(reader: &mut R, writer: &mut W) -> io::Result<u64>
where
R: Read,
W: Write,
{
let mut buf = unsafe {
#[allow(deprecated)]
let mut buf: [u8; super::DEFAULT_BUF_SIZE] = mem::uninitialized();
reader.initializer().initialize(&mut buf);
buf
};
let mut written = 0;
loop {
let len = match reader.read(&mut buf) {
Ok(0) => return Ok(written),
Ok(len) => len,
Err(ref e) if e.kind() == ErrorKind::Interrupted => continue,
Err(e) => return Err(e),
};
writer.write_all(&buf[..len])?;
written += len as u64;
}
}
/// A reader which is always at EOF.
///
/// This struct is generally created by calling [`empty`]. Please see
/// the documentation of [`empty()`][`empty`] for more details.
///
/// [`empty`]: fn.empty.html
pub struct Empty {
_priv: (),
}
/// Constructs a new handle to an empty reader.
///
/// All reads from the returned reader will return [`Ok`]`(0)`.
///
/// [`Ok`]: ../result/enum.Result.html#variant.Ok
///
/// # Examples
///
/// A slightly sad example of not reading anything into a buffer:
///
/// ```
/// use std::io::{self, Read};
///
/// let mut buffer = String::new();
/// io::empty().read_to_string(&mut buffer).unwrap();
/// assert!(buffer.is_empty());
/// ```
pub fn empty() -> Empty {
Empty { _priv: () }
}
impl Read for Empty {
#[inline]
fn read(&mut self, _buf: &mut [u8]) -> io::Result<usize> {
Ok(0)
}
#[inline]
unsafe fn initializer(&self) -> Initializer {
Initializer::nop()
}
}
#[cfg(feature="collections")]
impl BufRead for Empty {
#[inline]
fn fill_buf(&mut self) -> io::Result<&[u8]> {
Ok(&[])
}
#[inline]
fn consume(&mut self, _n: usize) {}
}
impl fmt::Debug for Empty {
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
f.pad("Empty { .. }")
}
}
/// A reader which yields one byte over and over and over and over and over and...
///
/// This struct is generally created by calling [`repeat`][repeat]. Please
/// see the documentation of `repeat()` for more details.
///
/// [repeat]: fn.repeat.html
pub struct Repeat {
byte: u8,
}
/// Creates an instance of a reader that infinitely repeats one byte.
///
/// All reads from this reader will succeed by filling the specified buffer with
/// the given byte.
///
/// # Examples
///
/// ```
/// use std::io::{self, Read};
///
/// let mut buffer = [0; 3];
/// io::repeat(0b101).read_exact(&mut buffer).unwrap();
/// assert_eq!(buffer, [0b101, 0b101, 0b101]);
/// ```
pub fn repeat(byte: u8) -> Repeat {
Repeat { byte }
}
impl Read for Repeat {
#[inline]
fn read(&mut self, buf: &mut [u8]) -> io::Result<usize> {
for slot in &mut *buf {
*slot = self.byte;
}
Ok(buf.len())
}
#[inline]
unsafe fn initializer(&self) -> Initializer {
Initializer::nop()
}
}
impl fmt::Debug for Repeat {
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
f.pad("Repeat { .. }")
}
}
/// A writer which will move data into the void.
///
/// This struct is generally created by calling [`sink`][sink]. Please
/// see the documentation of `sink()` for more details.
///
/// [sink]: fn.sink.html
pub struct Sink {
_priv: (),
}
/// Creates an instance of a writer which will successfully consume all data.
///
/// All calls to `write` on the returned instance will return `Ok(buf.len())`
/// and the contents of the buffer will not be inspected.
///
/// # Examples
///
/// ```rust
/// use std::io::{self, Write};
///
/// let buffer = vec![1, 2, 3, 5, 8];
/// let num_bytes = io::sink().write(&buffer).unwrap();
/// assert_eq!(num_bytes, 5);
/// ```
pub fn sink() -> Sink {
Sink { _priv: () }
}
impl Write for Sink {
#[inline]
fn write(&mut self, buf: &[u8]) -> io::Result<usize> {
Ok(buf.len())
}
#[inline]
fn flush(&mut self) -> io::Result<()> {
Ok(())
}
}
impl fmt::Debug for Sink {
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
f.pad("Sink { .. }")
}
}
#[cfg(test)]
mod tests {
use crate::io::prelude::*;
use crate::io::{copy, empty, repeat, sink};
#[test]
fn copy_copies() {
let mut r = repeat(0).take(4);
let mut w = sink();
assert_eq!(copy(&mut r, &mut w).unwrap(), 4);
let mut r = repeat(0).take(1 << 17);
assert_eq!(copy(&mut r as &mut dyn Read, &mut w as &mut dyn Write).unwrap(), 1 << 17);
}
#[test]
fn sink_sinks() {
let mut s = sink();
assert_eq!(s.write(&[]).unwrap(), 0);
assert_eq!(s.write(&[0]).unwrap(), 1);
assert_eq!(s.write(&[0; 1024]).unwrap(), 1024);
assert_eq!(s.by_ref().write(&[0; 1024]).unwrap(), 1024);
}
#[test]
fn empty_reads() {
let mut e = empty();
assert_eq!(e.read(&mut []).unwrap(), 0);
assert_eq!(e.read(&mut [0]).unwrap(), 0);
assert_eq!(e.read(&mut [0; 1024]).unwrap(), 0);
assert_eq!(e.by_ref().read(&mut [0; 1024]).unwrap(), 0);
}
#[test]
fn repeat_repeats() {
let mut r = repeat(4);
let mut b = [0; 1024];
assert_eq!(r.read(&mut b).unwrap(), 1024);
assert!(b.iter().all(|b| *b == 4));
}
#[test]
fn take_some_bytes() {
assert_eq!(repeat(4).take(100).bytes().count(), 100);
assert_eq!(repeat(4).take(100).bytes().next().unwrap().unwrap(), 4);
assert_eq!(repeat(1).take(10).chain(repeat(2).take(10)).bytes().count(), 20);
}
}

51
src/libcoreio/src/lib.rs Normal file
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@ -0,0 +1,51 @@
//! <p id="core_io-show-docblock"></p>
//! This is just a listing of the functionality available in this crate. See
//! the [std documentation](https://doc.rust-lang.org/nightly/std/io/index.html)
//! for a full description of the functionality.
#![allow(stable_features,unused_features)]
#![feature(question_mark,const_fn,copy_from_slice,try_from,str_internals,align_offset,slice_internals)]
#![cfg_attr(any(feature="alloc",feature="collections"),feature(alloc))]
#![cfg_attr(pattern_guards,feature(bind_by_move_pattern_guards,nll))]
#![cfg_attr(non_exhaustive,feature(non_exhaustive))]
#![cfg_attr(unicode,feature(str_char))]
#![cfg_attr(unicode,feature(unicode))]
#![no_std]
#[cfg_attr(feature="collections",macro_use)]
#[cfg_attr(feature="collections",allow(unused_imports))]
#[cfg(feature="collections")] extern crate alloc as collections;
#[cfg(feature="alloc")] extern crate alloc;
#[cfg(rustc_unicode)]
extern crate rustc_unicode;
#[cfg(std_unicode)]
extern crate std_unicode;
#[cfg(not(feature="collections"))]
pub type ErrorString = &'static str;
// Provide Box::new wrapper
#[cfg(not(feature="alloc"))]
struct FakeBox<T>(core::marker::PhantomData<T>);
#[cfg(not(feature="alloc"))]
impl<T> FakeBox<T> {
fn new(val: T) -> T {
val
}
}
// Needed for older compilers, to ignore vec!/format! macros in tests
#[cfg(not(feature="collections"))]
#[allow(unused)]
macro_rules! vec (
( $ elem : expr ; $ n : expr ) => { () };
( $ ( $ x : expr ) , * ) => { () };
( $ ( $ x : expr , ) * ) => { () };
);
#[cfg(not(feature="collections"))]
#[allow(unused)]
macro_rules! format {
( $ ( $ arg : tt ) * ) => { () };
}
mod io;
pub use io::*;

1
src/libdyld/Cargo.toml
View File

@ -8,4 +8,3 @@ name = "dyld"
[dependencies]
log = "0.4"
libcortex_a9 = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }

8
src/libdyld/src/file.rs
View File

@ -56,14 +56,6 @@ impl<'a> File<'a> {
})
}
pub fn section_headers<'b>(&'b self) -> impl Iterator<Item = Option<Elf32_Shdr>> + 'b
{
(0..self.ehdr.e_shnum).map(move |i| {
let shdr_off = self.ehdr.e_shoff as usize + mem::size_of::<Elf32_Shdr>() * i as usize;
self.read_unaligned::<Elf32_Shdr>(shdr_off)
})
}
pub fn dyn_header_vaddr(&self) -> Option<Range<usize>> {
self.program_headers()
.filter_map(|phdr| phdr)

75
src/libdyld/src/lib.rs
View File

@ -2,9 +2,8 @@
extern crate alloc;
extern crate log;
extern crate libcortex_a9;
use core::{convert, fmt, ops::Range, str};
use core::{convert, fmt, str};
use alloc::string::String;
use log::{debug, trace};
use elf::*;
@ -58,11 +57,43 @@ fn elf_hash(name: &[u8]) -> u32 {
h
}
// linker symbols
extern "C" {
#[no_mangle]
static __text_start: u32;
#[no_mangle]
static __text_end: u32;
#[no_mangle]
static __exidx_start: u32;
#[no_mangle]
static __exidx_end: u32;
}
static mut KERNEL_EXIDX_START: u32 = 0;
static mut KERNEL_EXIDX_END: u32 = 0;
#[no_mangle]
extern fn dl_unwind_find_exidx(pc: u32, len_ptr: *mut u32) -> u32 {
let length: u32;
let start: u32;
unsafe {
if (&__text_start as *const u32 as u32) <= pc && pc < (&__text_end as *const u32 as u32) {
length = (&__exidx_end - &__exidx_start) as u32;
start = &__exidx_start as *const u32 as u32;
} else {
// make sure that the kernel is loaded
assert_ne!(KERNEL_EXIDX_START, 0);
length = (KERNEL_EXIDX_END - KERNEL_EXIDX_START) / core::mem::size_of::<u32>() as u32;
start = KERNEL_EXIDX_START;
}
*len_ptr = length;
}
start
}
pub struct Library {
pub image: Image,
pub arch: Arch,
dyn_section: DynamicSection,
exidx: Range<usize>,
}
impl Library {
@ -132,15 +163,6 @@ impl Library {
Ok(self.strtab().get(offset..offset + size)
.ok_or("cannot read symbol name")?)
}
/// Rebind Rela by `name` to a new `addr`
pub fn rebind(&self, name: &[u8], addr: *const ()) -> Result<(), Error> {
reloc::rebind(self.arch, self, name, addr as Elf32_Word)
}
pub fn exidx(&self) -> &[u32] {
self.image.get_ref_slice_unchecked(&self.exidx)
}
}
pub fn load(
@ -193,21 +215,14 @@ pub fn load(
.ok_or("program header requests an out of bounds load (in target)")?;
dst.copy_from_slice(src);
}
_ => {}
}
}
let mut exidx = None;
// Obtain EXIDX
for shdr in file.section_headers() {
let shdr = shdr.ok_or("cannot read section header")?;
match shdr.sh_type as usize {
SHT_ARM_EXIDX => {
let range = shdr.sh_addr as usize..
(shdr.sh_addr + shdr.sh_size) as usize;
let _ = image.get(range.clone())
.ok_or("section header specifies EXIDX outside of image (in target)")?;
exidx = Some(range);
PT_ARM_EXIDX => {
let range = image.get(phdr.p_vaddr as usize..
(phdr.p_vaddr + phdr.p_filesz) as usize)
.ok_or("program header requests and out of bounds load (in target)")?;
unsafe {
KERNEL_EXIDX_START = range.as_ptr() as u32;
KERNEL_EXIDX_END = range.as_ptr().add(range.len()) as u32;
}
}
_ => {}
}
@ -220,10 +235,8 @@ pub fn load(
debug!("Relocating {} rela, {} rel, {} pltrel",
dyn_section.rela.len(), dyn_section.rel.len(), dyn_section.pltrel.len());
let lib = Library {
arch,
image,
dyn_section,
exidx: exidx.ok_or("no EXIDX section")?,
dyn_section
};
for rela in lib.rela() {

35
src/libdyld/src/reloc.rs
View File

@ -7,10 +7,6 @@ use super::{
image::Image,
Library,
};
use libcortex_a9::{
cache::{dcci_slice, iciallu, bpiall},
asm::{dsb, isb},
};
pub trait Relocatable {
fn offset(&self) -> usize;
@ -137,34 +133,3 @@ pub fn relocate<R: Relocatable>(
lib.image.write(rel.offset(), value)
}
pub fn rebind(
arch: Arch, lib: &Library, name: &[u8], value: Elf32_Word
) -> Result<(), Error> {
for rela in lib.pltrel() {
let rel_type = RelType::new(arch, rela.type_info())
.ok_or("unsupported relocation type")?;
match rel_type {
RelType::Lookup => {
let sym = lib.symtab().get(ELF32_R_SYM(rela.r_info) as usize)
.ok_or("symbol out of bounds of symbol table")?;
let sym_name = lib.name_starting_at(sym.st_name as usize)?;
if sym_name == name {
lib.image.write(rela.offset(), value)?
}
}
// No associated symbols for other relocation types.
_ => {}
}
}
// FIXME: the cache maintainance operations may be more than enough,
// may cause performance degradation.
dcci_slice(lib.image.data);
iciallu();
bpiall();
dsb();
isb();
Ok(())
}

5
src/llvm_libunwind/src/Unwind-EHABI.cpp
View File

@ -551,7 +551,6 @@ static _Unwind_Reason_Code unwind_phase2(unw_context_t *uc, unw_cursor_t *cursor
static_cast<void *>(exception_object));
int frame_count = 0;
unw_word_t prev_sp = 0x0;
// Walk each frame until we reach where search phase said to stop.
while (true) {
// Ask libunwind to get next frame (skip over first which is
@ -577,10 +576,6 @@ static _Unwind_Reason_Code unwind_phase2(unw_context_t *uc, unw_cursor_t *cursor
unw_word_t sp;
unw_proc_info_t frameInfo;
__unw_get_reg(cursor, UNW_REG_SP, &sp);
if (sp == prev_sp) {
return _URC_END_OF_STACK;
}
prev_sp = sp;
if (__unw_get_proc_info(cursor, &frameInfo) != UNW_ESUCCESS) {
_LIBUNWIND_TRACE_UNWINDING(
"unwind_phase2(ex_ojb=%p): __unw_get_proc_info "

14
src/runtime/Cargo.toml
View File

@ -21,16 +21,14 @@ byteorder = { version = "1.3", default-features = false }
void = { version = "1", default-features = false }
futures = { version = "0.3", default-features = false, features = ["async-await"] }
async-recursion = "0.3"
fatfs = { version = "0.3", features = ["core_io"], default-features = false }
log_buffer = { version = "1.2" }
libm = { version = "0.2", features = ["unstable"] }
vcell = "0.1"
libboard_zynq = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git", features = ["ipv6"]}
libsupport_zynq = { default-features = false, features = ["alloc_core"], git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
libcortex_a9 = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
libasync = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
libregister = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
libconfig = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git", features = ["ipv6"] }
libboard_zynq = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
libsupport_zynq = { default-features = false, git = "https://git.m-labs.hk/M-Labs/zc706.git" }
libcortex_a9 = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
libasync = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
libregister = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
dyld = { path = "../libdyld" }
dwarf = { path = "../libdwarf" }

10
src/runtime/build.rs
View File

@ -1,7 +1,6 @@
use std::env;
use std::fs::File;
use std::io::Write;
use std::io::{BufRead, BufReader};
use std::path::PathBuf;
fn main() {
@ -16,13 +15,4 @@ fn main() {
// Only re-run the build script when link.x is changed,
// instead of when any part of the source code changes.
println!("cargo:rerun-if-changed=link.x");
// Handle rustc-cfg file
let cfg_path = "../../build/rustc-cfg";
println!("cargo:rerun-if-changed={}", cfg_path);
let f = BufReader::new(File::open(cfg_path).unwrap());
for line in f.lines() {
println!("cargo:rustc-cfg={}", line.unwrap());
}
}

9
src/runtime/link.x
View File

@ -48,12 +48,9 @@ SECTIONS
.heap (NOLOAD) : ALIGN(8)
{
__heap0_start = .;
. += 0x8000000;
__heap0_end = .;
__heap1_start = .;
. += 0x8000000;
__heap1_end = .;
__heap_start = .;
. += 0x1000000;
__heap_end = .;
} > SDRAM
.stack1 (NOLOAD) : ALIGN(8)

111
src/runtime/src/analyzer.rs
View File

@ -1,111 +0,0 @@
use libasync::{smoltcp::TcpStream, task};
use libboard_zynq::smoltcp::Error;
use libcortex_a9::cache;
use log::{debug, info, warn};
use crate::proto_async::*;
use crate::pl;
const BUFFER_SIZE: usize = 512 * 1024;
#[repr(align(64))]
struct Buffer {
data: [u8; BUFFER_SIZE],
}
static mut BUFFER: Buffer = Buffer {
data: [0; BUFFER_SIZE]
};
fn arm() {
debug!("arming RTIO analyzer");
unsafe {
let base_addr = &mut BUFFER.data[0] as *mut _ as usize;
let last_addr = &mut BUFFER.data[BUFFER_SIZE - 1] as *mut _ as usize;
pl::csr::rtio_analyzer::message_encoder_overflow_reset_write(1);
pl::csr::rtio_analyzer::dma_base_address_write(base_addr as u32);
pl::csr::rtio_analyzer::dma_last_address_write(last_addr as u32);
pl::csr::rtio_analyzer::dma_reset_write(1);
pl::csr::rtio_analyzer::enable_write(1);
}
}
fn disarm() {
debug!("disarming RTIO analyzer");
unsafe {
pl::csr::rtio_analyzer::enable_write(0);
while pl::csr::rtio_analyzer::busy_read() != 0 {}
cache::dcci_slice(&BUFFER.data);
}
debug!("RTIO analyzer disarmed");
}
#[derive(Debug)]
struct Header {
sent_bytes: u32,
total_byte_count: u64,
error_occurred: bool,
log_channel: u8,
dds_onehot_sel: bool
}
async fn write_header(stream: &mut TcpStream, header: &Header) -> Result<(), Error> {
write_i32(stream, header.sent_bytes as i32).await?;
write_i64(stream, header.total_byte_count as i64).await?;
write_i8(stream, header.error_occurred as i8).await?;
write_i8(stream, header.log_channel as i8).await?;
write_i8(stream, header.dds_onehot_sel as i8).await?;
Ok(())
}
async fn handle_connection(stream: &mut TcpStream) -> Result<(), Error> {
info!("received connection");
let data = unsafe { &BUFFER.data[..] };
let overflow_occurred = unsafe { pl::csr::rtio_analyzer::message_encoder_overflow_read() != 0 };
let bus_error_occurred = unsafe { pl::csr::rtio_analyzer::dma_bus_error_read() != 0 };
let total_byte_count = unsafe { pl::csr::rtio_analyzer::dma_byte_count_read() as u64 };
let pointer = (total_byte_count % BUFFER_SIZE as u64) as usize;
let wraparound = total_byte_count >= BUFFER_SIZE as u64;
if overflow_occurred {
warn!("overflow occured");
}
if bus_error_occurred {
warn!("bus error occured");
}
let header = Header {
total_byte_count: total_byte_count,
sent_bytes: if wraparound { BUFFER_SIZE as u32 } else { total_byte_count as u32 },
error_occurred: overflow_occurred | bus_error_occurred,
log_channel: pl::csr::CONFIG_RTIO_LOG_CHANNEL as u8,
dds_onehot_sel: true // kept for backward compatibility of analyzer dumps
};
debug!("{:?}", header);
write_header(stream, &header).await?;
if wraparound {
stream.send(data[pointer..].iter().copied()).await?;
stream.send(data[..pointer].iter().copied()).await?;
} else {
stream.send(data[..pointer].iter().copied()).await?;
}
Ok(())
}
pub fn start() {
task::spawn(async move {
loop {
arm();
let mut stream = TcpStream::accept(1382, 2048, 2048).await.unwrap();
disarm();
let _ = handle_connection(&mut stream)
.await
.map_err(|e| warn!("connection terminated: {:?}", e));
let _ = stream.flush().await;
let _ = stream.close().await;
}
});
}

148
src/runtime/src/comms.rs
View File

@ -1,7 +1,9 @@
use core::fmt;
use core::cell::RefCell;
use core::str::Utf8Error;
use alloc::{vec, vec::Vec, string::String, collections::BTreeMap, rc::Rc};
use alloc::rc::Rc;
use alloc::sync::Arc;
use alloc::{vec, vec::Vec, string::String};
use log::{info, warn, error};
use num_derive::{FromPrimitive, ToPrimitive};
@ -17,17 +19,14 @@ use libboard_zynq::{
},
timer::GlobalTimer,
};
use libcortex_a9::{semaphore::Semaphore, mutex::Mutex, sync_channel::{Sender, Receiver}};
use futures::{select_biased, future::FutureExt};
use libasync::{smoltcp::{Sockets, TcpStream}, task};
use libconfig::{Config, net_settings};
use crate::config;
use crate::net_settings;
use crate::proto_async::*;
use crate::kernel;
use crate::rpc;
use crate::moninj;
use crate::mgmt;
use crate::analyzer;
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
@ -81,11 +80,8 @@ enum Reply {
ClockFailure = 15,
}
static CACHE_STORE: Mutex<BTreeMap<String, Vec<i32>>> = Mutex::new(BTreeMap::new());
static DMA_RECORD_STORE: Mutex<BTreeMap<String, (Vec<u8>, i64)>> = Mutex::new(BTreeMap::new());
async fn write_header(stream: &TcpStream, reply: Reply) -> Result<()> {
stream.send_slice(&[0x5a, 0x5a, 0x5a, 0x5a, reply.to_u8().unwrap()]).await?;
stream.send([0x5a, 0x5a, 0x5a, 0x5a, reply.to_u8().unwrap()].iter().copied()).await?;
Ok(())
}
@ -124,40 +120,11 @@ async fn read_string(stream: &TcpStream, max_length: usize) -> Result<String> {
Ok(String::from_utf8(bytes).map_err(|err| Error::Utf8Error(err.utf8_error()))?)
}
const RETRY_LIMIT: usize = 100;
async fn fast_send(sender: &mut Sender<'_, kernel::Message>, content: kernel::Message) {
let mut content = content;
for _ in 0..RETRY_LIMIT {
match sender.try_send(content) {
Ok(()) => {
return
},
Err(v) => {
content = v;
}
}
}
sender.async_send(content).await;
}
async fn fast_recv(receiver: &mut Receiver<'_, kernel::Message>) -> kernel::Message {
for _ in 0..RETRY_LIMIT {
match receiver.try_recv() {
Ok(v) => {
return v;
},
Err(()) => ()
}
}
receiver.async_recv().await
}
async fn handle_run_kernel(stream: Option<&TcpStream>, control: &Rc<RefCell<kernel::Control>>) -> Result<()> {
control.borrow_mut().tx.async_send(kernel::Message::StartRequest).await;
loop {
let reply = control.borrow_mut().rx.async_recv().await;
match reply {
match *reply {
kernel::Message::RpcSend { is_async, data } => {
if stream.is_none() {
error!("Unexpected RPC from startup/idle kernel!");
@ -166,13 +133,13 @@ async fn handle_run_kernel(stream: Option<&TcpStream>, control: &Rc<RefCell<kern
let stream = stream.unwrap();
write_header(stream, Reply::RPCRequest).await?;
write_bool(stream, is_async).await?;
stream.send_slice(&data).await?;
stream.send(data.iter().copied()).await?;
if !is_async {
let host_request = read_request(stream, false).await?.unwrap();
match host_request {
Request::RPCReply => {
let tag = read_bytes(stream, 512).await?;
let slot = match fast_recv(&mut control.borrow_mut().rx).await {
let slot = match *control.borrow_mut().rx.async_recv().await {
kernel::Message::RpcRecvRequest(slot) => slot,
other => panic!("expected root value slot from core1, not {:?}", other),
};
@ -185,8 +152,8 @@ async fn handle_run_kernel(stream: Option<&TcpStream>, control: &Rc<RefCell<kern
0 as *mut ()
} else {
let mut control = control.borrow_mut();
fast_send(&mut control.tx, kernel::Message::RpcRecvReply(Ok(size))).await;
match fast_recv(&mut control.rx).await {
control.tx.async_send(kernel::Message::RpcRecvReply(Ok(size))).await;
match *control.rx.async_recv().await {
kernel::Message::RpcRecvRequest(slot) => slot,
other => panic!("expected nested value slot from kernel CPU, not {:?}", other),
}
@ -197,7 +164,7 @@ async fn handle_run_kernel(stream: Option<&TcpStream>, control: &Rc<RefCell<kern
},
Request::RPCException => {
let mut control = control.borrow_mut();
match control.rx.async_recv().await {
match *control.rx.async_recv().await {
kernel::Message::RpcRecvRequest(_) => (),
other => panic!("expected (ignored) root value slot from kernel CPU, not {:?}", other),
}
@ -253,25 +220,6 @@ async fn handle_run_kernel(stream: Option<&TcpStream>, control: &Rc<RefCell<kern
}
break;
}
kernel::Message::CachePutRequest(key, value) => {
CACHE_STORE.lock().insert(key, value);
},
kernel::Message::CacheGetRequest(key) => {
const DEFAULT: Vec<i32> = Vec::new();
let value = CACHE_STORE.lock().get(&key).unwrap_or(&DEFAULT).clone();
control.borrow_mut().tx.async_send(kernel::Message::CacheGetReply(value)).await;
},
kernel::Message::DmaPutRequest(recorder) => {
DMA_RECORD_STORE.lock().insert(recorder.name, (recorder.buffer, recorder.duration));
},
kernel::Message::DmaEraseRequest(name) => {
// prevent possible OOM when we have large DMA record replacement.
DMA_RECORD_STORE.lock().remove(&name);
},
kernel::Message::DmaGetRequest(name) => {
let result = DMA_RECORD_STORE.lock().get(&name).map(|v| v.clone());
control.borrow_mut().tx.async_send(kernel::Message::DmaGetReply(result)).await;
},
_ => {
panic!("unexpected message from core1 while kernel was running: {:?}", reply);
}
@ -281,12 +229,12 @@ async fn handle_run_kernel(stream: Option<&TcpStream>, control: &Rc<RefCell<kern
}
async fn load_kernel(buffer: &Vec<u8>, control: &Rc<RefCell<kernel::Control>>, stream: Option<&TcpStream>) -> Result<()> {
async fn load_kernel(buffer: Vec<u8>, control: &Rc<RefCell<kernel::Control>>, stream: Option<&TcpStream>) -> Result<()> {
let mut control = control.borrow_mut();
control.restart();
control.tx.async_send(kernel::Message::LoadRequest(buffer.to_vec())).await;
control.tx.async_send(kernel::Message::LoadRequest(Arc::new(buffer))).await;
let reply = control.rx.async_recv().await;
match reply {
match *reply {
kernel::Message::LoadCompleted => {
if let Some(stream) = stream {
write_header(stream, Reply::LoadCompleted).await?;
@ -314,9 +262,8 @@ async fn load_kernel(buffer: &Vec<u8>, control: &Rc<RefCell<kernel::Control>>, s
}
async fn handle_connection(stream: &TcpStream, control: Rc<RefCell<kernel::Control>>) -> Result<()> {
if !expect(stream, b"ARTIQ coredev\n").await? {
return Err(Error::UnexpectedPattern);
}
expect(stream, b"ARTIQ coredev\n").await?;
info!("received connection");
loop {
let request = read_request(stream, true).await?;
if request.is_none() {
@ -326,11 +273,11 @@ async fn handle_connection(stream: &TcpStream, control: Rc<RefCell<kernel::Contr
match request {
Request::SystemInfo => {
write_header(stream, Reply::SystemInfo).await?;
stream.send_slice("ARZQ".as_bytes()).await?;
stream.send("ARZQ".bytes()).await?;
},
Request::LoadKernel => {
let buffer = read_bytes(stream, 1024*1024).await?;
load_kernel(&buffer, &control, Some(stream)).await?;
load_kernel(buffer, &control, Some(stream)).await?;
},
Request::RunKernel => {
handle_run_kernel(Some(stream), &control).await?;
@ -343,15 +290,15 @@ async fn handle_connection(stream: &TcpStream, control: Rc<RefCell<kernel::Contr
}
}
pub fn main(timer: GlobalTimer, cfg: &Config) {
pub fn main(timer: GlobalTimer, cfg: &config::Config) {
let net_addresses = net_settings::get_adresses(cfg);
info!("network addresses: {}", net_addresses);
let eth = zynq::eth::Eth::eth0(net_addresses.hardware_addr.0.clone());
const RX_LEN: usize = 64;
let eth = zynq::eth::Eth::default(net_addresses.hardware_addr.0.clone());
const RX_LEN: usize = 8;
// Number of transmission buffers (minimum is two because with
// one, duplicate packet transmission occurs)
const TX_LEN: usize = 64;
const TX_LEN: usize = 8;
let eth = eth.start_rx(RX_LEN);
let mut eth = eth.start_tx(TX_LEN);
@ -384,15 +331,10 @@ pub fn main(timer: GlobalTimer, cfg: &Config) {
Sockets::init(32);
mgmt::start(*cfg);
analyzer::start();
moninj::start(timer);
let control: Rc<RefCell<kernel::Control>> = Rc::new(RefCell::new(kernel::Control::start()));
let idle_kernel = Rc::new(cfg.read("idle").ok());
if let Ok(buffer) = cfg.read("startup") {
info!("Loading startup kernel...");
if let Ok(()) = task::block_on(load_kernel(&buffer, &control, None)) {
if let Ok(()) = task::block_on(load_kernel(buffer, &control, None)) {
info!("Starting startup kernel...");
let _ = task::block_on(handle_run_kernel(None, &control));
info!("Startup kernel finished!");
@ -402,49 +344,21 @@ pub fn main(timer: GlobalTimer, cfg: &Config) {
}
task::spawn(async move {
let connection = Rc::new(Semaphore::new(1, 1));
let terminate = Rc::new(Semaphore::new(0, 1));
loop {
let stream = TcpStream::accept(1381, 0x10_000, 0x10_000).await.unwrap();
if connection.try_wait().is_none() {
// there is an existing connection
terminate.signal();
connection.async_wait().await;
}
let stream = TcpStream::accept(1381, 2048, 2048).await.unwrap();
let control = control.clone();
let idle_kernel = idle_kernel.clone();
let connection = connection.clone();
let terminate = terminate.clone();
// we make sure the value of terminate is 0 before we start
let _ = terminate.try_wait();
task::spawn(async move {
select_biased! {
_ = (async {
let _ = handle_connection(&stream, control.clone())
.await
.map_err(|e| warn!("connection terminated: {}", e));
if let Some(buffer) = &*idle_kernel {
info!("Loading idle kernel");
let _ = load_kernel(&buffer, &control, None)
.await.map_err(|e| warn!("error loading idle kernel"));
info!("Running idle kernel");
let _ = handle_run_kernel(None, &control)
.await.map_err(|e| warn!("error running idle kernel"));
info!("Idle kernel terminated");
}
}).fuse() => (),
_ = terminate.async_wait().fuse() => ()
}
connection.signal();
task::spawn(async {
let _ = handle_connection(&stream, control)
.await
.map_err(|e| warn!("connection terminated: {}", e));
let _ = stream.flush().await;
let _ = stream.abort().await;
});
}
});
moninj::start(timer);
Sockets::run(&mut iface, || {
Instant::from_millis(timer.get_time().0 as i32)
});

106
src/runtime/src/config.rs Normal file
View File

@ -0,0 +1,106 @@
use crate::sd_reader;
use core::fmt;
use alloc::{string::FromUtf8Error, string::String, vec::Vec};
use core_io::{self as io, BufRead, BufReader, Read};
use libboard_zynq::sdio;
#[derive(Debug)]
pub enum Error<'a> {
SdError(sdio::sd_card::CardInitializationError),
IoError(io::Error),
Utf8Error(FromUtf8Error),
KeyNotFoundError(&'a str),
NoConfig,
}
pub type Result<'a, T> = core::result::Result<T, Error<'a>>;
impl<'a> fmt::Display for Error<'a> {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
match self {
Error::SdError(error) => write!(f, "SD error: {}", error),
Error::IoError(error) => write!(f, "I/O error: {}", error),
Error::Utf8Error(error) => write!(f, "UTF-8 error: {}", error),
Error::KeyNotFoundError(name) => write!(f, "Configuration key `{}` not found", name),
Error::NoConfig => write!(f, "Configuration not present"),
}
}
}
impl<'a> From<sdio::sd_card::CardInitializationError> for Error<'a> {
fn from(error: sdio::sd_card::CardInitializationError) -> Self {
Error::SdError(error)
}
}
impl<'a> From<io::Error> for Error<'a> {
fn from(error: io::Error) -> Self {
Error::IoError(error)
}
}
impl<'a> From<FromUtf8Error> for Error<'a> {
fn from(error: FromUtf8Error) -> Self {
Error::Utf8Error(error)
}
}
fn parse_config<'a>(
key: &'a str,
buffer: &mut Vec<u8>,
file: fatfs::File<sd_reader::SdReader>,
) -> Result<'a, ()> {
let prefix = [key, "="].concat();
for line in BufReader::new(file).lines() {
let line = line?;
if line.starts_with(&prefix) {
buffer.extend(line[prefix.len()..].as_bytes());
return Ok(());
}
}
Err(Error::KeyNotFoundError(key))
}
pub struct Config {
fs: Option<fatfs::FileSystem<sd_reader::SdReader>>,
}
impl Config {
pub fn new() -> Result<'static, Self> {
let sdio = sdio::SDIO::sdio0(true);
if !sdio.is_card_inserted() {
Err(sdio::sd_card::CardInitializationError::NoCardInserted)?;
}
let sd = sdio::sd_card::SdCard::from_sdio(sdio)?;
let reader = sd_reader::SdReader::new(sd);
let fs = reader.mount_fatfs(sd_reader::PartitionEntry::Entry1)?;
Ok(Config { fs: Some(fs) })
}
pub fn new_dummy() -> Self {
Config { fs: None }
}
pub fn read<'b>(&self, key: &'b str) -> Result<'b, Vec<u8>> {
if let Some(fs) = &self.fs {
let root_dir = fs.root_dir();
let mut buffer: Vec<u8> = Vec::new();
match root_dir.open_file(&["/CONFIG/", key, ".BIN"].concat()) {
Ok(mut f) => f.read_to_end(&mut buffer).map(|_| ())?,
Err(_) => match root_dir.open_file("/CONFIG.TXT") {
Ok(f) => parse_config(key, &mut buffer, f)?,
Err(_) => return Err(Error::KeyNotFoundError(key)),
},
};
Ok(buffer)
} else {
Err(Error::NoConfig)
}
}
pub fn read_str<'b>(&self, key: &'b str) -> Result<'b, String> {
Ok(String::from_utf8(self.read(key)?)?)
}
}

21
src/runtime/src/eh_artiq.rs
View File

@ -128,15 +128,8 @@ pub unsafe fn artiq_personality(state: uw::_Unwind_State,
let exception = &exception_info.exception.unwrap();
if search_phase {
match eh_action {
EHAction::None => return continue_unwind(exception_object, context),
// Actually, cleanup should not return handler found, this is to workaround
// the issue of terminating directly when no catch cause is found while
// having some cleanup routines defined by finally.
// The best way to handle this is to force unwind the stack in the raise
// function when end of stack is reached, and call terminate at the end of
// the unwind. Unfortunately, there is no forced unwind function defined
// for EHABI, and I have no idea how to implement that, so this is a hack.
EHAction::Cleanup(_) => return uw::_URC_HANDLER_FOUND,
EHAction::None |
EHAction::Cleanup(_) => return continue_unwind(exception_object, context),
EHAction::Catch(_) => {
// EHABI requires the personality routine to update the
// SP value in the barrier cache of the exception object.
@ -202,9 +195,10 @@ static mut INFLIGHT: ExceptionInfo = ExceptionInfo {
};
pub unsafe extern fn raise(exception: *const Exception) -> ! {
// Zing! The Exception<'a> to Exception<'static> transmute is not really sound in case
// the exception is ever captured. Fortunately, they currently aren't, and we save
// on the hassle of having to allocate exceptions somewhere except on stack.
trace!("Trying to raise exception");
// FIXME: unsound transmute
// This would cause stack memory corruption.
INFLIGHT.exception = Some(mem::transmute::<Exception, Exception<'static>>(*exception));
INFLIGHT.handled = false;
@ -225,8 +219,9 @@ pub unsafe extern fn raise(exception: *const Exception) -> ! {
pub unsafe extern fn reraise() -> ! {
use cslice::AsCSlice;
// Reraise is basically cxa_rethrow, which calls _Unwind_Resume_or_Rethrow,
// which for EHABI would always call _Unwind_RaiseException.
trace!("Re-raise");
// current implementation uses raise as _Unwind_Resume is not working now
// would debug that later.
match INFLIGHT.exception {
Some(ref exception) => raise(exception),
None => raise(&Exception {

68
src/runtime/src/i2c.rs
View File

@ -1,68 +0,0 @@
use libboard_zynq;
use crate::artiq_raise;
static mut I2C_BUS: Option<libboard_zynq::i2c::I2c> = None;
pub extern fn start(busno: i32) {
if busno > 0 {
artiq_raise!("I2CError", "I2C bus could not be accessed");
}
unsafe {
if (&mut I2C_BUS).as_mut().unwrap().start().is_err() {
artiq_raise!("I2CError", "I2C start failed");
}
}
}
pub extern fn restart(busno: i32) {
if busno > 0 {
artiq_raise!("I2CError", "I2C bus could not be accessed");
}
unsafe {
if (&mut I2C_BUS).as_mut().unwrap().restart().is_err() {
artiq_raise!("I2CError", "I2C restart failed");
}
}
}
pub extern fn stop(busno: i32) {
if busno > 0 {
artiq_raise!("I2CError", "I2C bus could not be accessed");
}
unsafe {
if (&mut I2C_BUS).as_mut().unwrap().stop().is_err() {
artiq_raise!("I2CError", "I2C stop failed");
}
}
}
pub extern fn write(busno: i32, data: i32) -> bool {
if busno > 0 {
artiq_raise!("I2CError", "I2C bus could not be accessed");
}
unsafe {
match (&mut I2C_BUS).as_mut().unwrap().write(data as u8) {
Ok(r) => r,
Err(_) => artiq_raise!("I2CError", "I2C write failed"),
}
}
}
pub extern fn read(busno: i32, ack: bool) -> i32 {
if busno > 0 {
artiq_raise!("I2CError", "I2C bus could not be accessed");
}
unsafe {
match (&mut I2C_BUS).as_mut().unwrap().read(ack) {
Ok(r) => r as i32,
Err(_) => artiq_raise!("I2CError", "I2C read failed"),
}
}
}
pub fn init() {
let mut i2c = libboard_zynq::i2c::I2c::i2c0();
i2c.init().expect("I2C bus initialization failed");
unsafe { I2C_BUS = Some(i2c) };
}

47
src/runtime/src/irq.rs
View File

@ -1,47 +0,0 @@
use libboard_zynq::{gic, mpcore, println, stdio};
use libcortex_a9::{
asm,
regs::{MPIDR, SP},
spin_lock_yield, notify_spin_lock
};
use libregister::{RegisterR, RegisterW};
use core::sync::atomic::{AtomicBool, Ordering};
extern "C" {
static mut __stack1_start: u32;
fn main_core1() -> !;
}
static CORE1_RESTART: AtomicBool = AtomicBool::new(false);
#[link_section = ".text.boot"]
#[no_mangle]
#[naked]
pub unsafe extern "C" fn IRQ() {
if MPIDR.read().cpu_id() == 1 {
let mpcore = mpcore::RegisterBlock::mpcore();
let mut gic = gic::InterruptController::gic(mpcore);
let id = gic.get_interrupt_id();
if id.0 == 0 {
gic.end_interrupt(id);
asm::exit_irq();
SP.write(&mut __stack1_start as *mut _ as u32);
asm::enable_irq();
CORE1_RESTART.store(false, Ordering::Relaxed);
notify_spin_lock();
main_core1();
}
}
stdio::drop_uart();
println!("IRQ");
loop {}
}
pub fn restart_core1() {
let mut interrupt_controller = gic::InterruptController::gic(mpcore::RegisterBlock::mpcore());
CORE1_RESTART.store(true, Ordering::Relaxed);
interrupt_controller.send_sgi(gic::InterruptId(0), gic::CPUCore::Core1.into());
while CORE1_RESTART.load(Ordering::Relaxed) {
spin_lock_yield();
}
}

153
src/runtime/src/kernel/api.rs
View File

@ -1,45 +1,6 @@
use core::ffi::VaList;
use core::ptr;
use core::str;
use libc::{c_char, c_int, size_t};
use libm;
use log::{info, warn};
use alloc::vec;
use crate::eh_artiq;
use crate::rtio;
use crate::i2c;
use super::rpc::{rpc_send, rpc_send_async, rpc_recv};
use super::dma;
use super::cache;
extern "C" {
fn vsnprintf_(buffer: *mut c_char, count: size_t, format: *const c_char, va: VaList) -> c_int;
}
unsafe extern fn core_log(fmt: *const c_char, mut args: ...) {
let size = vsnprintf_(ptr::null_mut(), 0, fmt, args.as_va_list()) as usize;
let mut buf = vec![0; size + 1];
vsnprintf_(buf.as_mut_ptr() as *mut i8, size + 1, fmt, args.as_va_list());
let buf: &[u8] = &buf.as_slice()[..size-1]; // strip \n and NUL
match str::from_utf8(buf) {
Ok(s) => info!("kernel: {}", s),
Err(e) => {
info!("kernel: {}", (str::from_utf8(&buf[..e.valid_up_to()]).unwrap()));
warn!("kernel: invalid utf-8");
}
}
}
unsafe extern fn rtio_log(fmt: *const c_char, mut args: ...) {
let size = vsnprintf_(ptr::null_mut(), 0, fmt, args.as_va_list()) as usize;
let mut buf = vec![0; size + 1];
vsnprintf_(buf.as_mut_ptr(), size + 1, fmt, args.as_va_list());
rtio::write_log(buf.as_slice());
}
macro_rules! api {
($i:ident) => ({
@ -55,15 +16,6 @@ macro_rules! api {
}
}
macro_rules! api_libm_f64f64 {
($i:ident) => ({
extern fn $i(x: f64) -> f64 {
libm::$i(x)
}
api!($i = $i)
})
}
pub fn resolve(required: &[u8]) -> Option<u32> {
let api = &[
// timing
@ -86,28 +38,6 @@ pub fn resolve(required: &[u8]) -> Option<u32> {
api!(rtio_input_data = rtio::input_data),
api!(rtio_input_timestamped_data = rtio::input_timestamped_data),
// log
api!(core_log = core_log),
api!(rtio_log = rtio_log),
// rtio dma
api!(dma_record_start = dma::dma_record_start),
api!(dma_record_stop = dma::dma_record_stop),
api!(dma_erase = dma::dma_erase),
api!(dma_retrieve = dma::dma_retrieve),
api!(dma_playback = dma::dma_playback),
// cache
api!(cache_get = cache::get),
api!(cache_put = cache::put),
// i2c
api!(i2c_start = i2c::start),
api!(i2c_restart = i2c::restart),
api!(i2c_stop = i2c::stop),
api!(i2c_write = i2c::write),
api!(i2c_read = i2c::read),
// Double-precision floating-point arithmetic helper functions
// RTABI chapter 4.1.2, Table 2
api!(__aeabi_dadd),
@ -171,7 +101,6 @@ pub fn resolve(required: &[u8]) -> Option<u32> {
// RTABI chapter 4.3.1
api!(__aeabi_idiv),
api!(__aeabi_ldivmod),
api!(__aeabi_idivmod),
api!(__aeabi_uidiv),
api!(__aeabi_uldivmod),
// 4.3.4 Memory copying, clearing, and setting
@ -187,96 +116,14 @@ pub fn resolve(required: &[u8]) -> Option<u32> {
api!(__aeabi_memclr8),
api!(__aeabi_memclr4),
api!(__aeabi_memclr),
// libc
api!(memcmp, extern { fn memcmp(a: *const u8, b: *mut u8, size: usize); }),
// exceptions
api!(_Unwind_Resume = unwind::_Unwind_Resume),
api!(__artiq_personality = eh_artiq::artiq_personality),
api!(__artiq_raise = eh_artiq::raise),
api!(__artiq_reraise = eh_artiq::reraise),
// Implementations for LLVM math intrinsics
api!(__powidf2),
// libm
api_libm_f64f64!(acos),
api_libm_f64f64!(acosh),
api_libm_f64f64!(asin),
api_libm_f64f64!(asinh),
api_libm_f64f64!(atan),
{
extern fn atan2(y: f64, x: f64) -> f64 {
libm::atan2(y, x)
}
api!(atan2 = atan2)
},
api_libm_f64f64!(atanh),
api_libm_f64f64!(cbrt),
api_libm_f64f64!(ceil),
api_libm_f64f64!(cos),
api_libm_f64f64!(cosh),
api_libm_f64f64!(erf),
api_libm_f64f64!(erfc),
api_libm_f64f64!(exp),
api_libm_f64f64!(exp2),
api_libm_f64f64!(exp10),
api_libm_f64f64!(expm1),
api_libm_f64f64!(fabs),
api_libm_f64f64!(floor),
{
extern fn fma(x: f64, y: f64, z: f64) -> f64 {
libm::fma(x, y, z)
}
api!(fma = fma)
},
{
extern fn fmod(x: f64, y: f64) -> f64 {
libm::fmod(x, y)
}
api!(fmod = fmod)
},
{
extern fn hypot(x: f64, y: f64) -> f64 {
libm::hypot(x, y)
}
api!(hypot = hypot)
},
api_libm_f64f64!(j0),
api_libm_f64f64!(j1),
{
extern fn jn(n: i32, x: f64) -> f64 {
libm::jn(n, x)
}
api!(jn = jn)
},
api_libm_f64f64!(lgamma),
api_libm_f64f64!(log),
api_libm_f64f64!(log2),
api_libm_f64f64!(log10),
{
extern fn pow(x: f64, y: f64) -> f64 {
libm::pow(x, y)
}
api!(pow = pow)
},
api_libm_f64f64!(round),
api_libm_f64f64!(sin),
api_libm_f64f64!(sinh),
api_libm_f64f64!(sqrt),
api_libm_f64f64!(tan),
api_libm_f64f64!(tanh),
api_libm_f64f64!(tgamma),
api_libm_f64f64!(trunc),
api_libm_f64f64!(y0),
api_libm_f64f64!(y1),
{
extern fn yn(n: i32, x: f64) -> f64 {
libm::yn(n, x)
}
api!(yn = yn)
},
];
api.iter()
.find(|&&(exported, _)| exported.as_bytes() == required)

30
src/runtime/src/kernel/cache.rs
View File

@ -1,30 +0,0 @@
use alloc::string::String;
use cslice::{CSlice, AsCSlice};
use core::mem::{transmute, forget};
use super::{KERNEL_CHANNEL_0TO1, KERNEL_CHANNEL_1TO0, Message};
pub extern fn get(key: CSlice<u8>) -> CSlice<'static, i32> {
let key = String::from_utf8(key.as_ref().to_vec()).unwrap();
unsafe {
KERNEL_CHANNEL_1TO0.as_mut().unwrap().send(Message::CacheGetRequest(key));
let msg = KERNEL_CHANNEL_0TO1.as_mut().unwrap().recv();
if let Message::CacheGetReply(v) = msg {
let slice = transmute(v.as_c_slice());
// we intentionally leak the memory here,
// which does not matter as core1 would restart
forget(v);
slice
} else {
panic!("Expected CacheGetReply for CacheGetRequest");
}
}
}
pub extern fn put(key: CSlice<u8>, list: CSlice<i32>) {
let key = String::from_utf8(key.as_ref().to_vec()).unwrap();
let value = list.as_ref().to_vec();
unsafe {
KERNEL_CHANNEL_1TO0.as_mut().unwrap().send(Message::CachePutRequest(key, value));
}
}

61
src/runtime/src/kernel/control.rs
View File

@ -1,56 +1,41 @@
use libcortex_a9::sync_channel::{Sender, Receiver};
use libcortex_a9::sync_channel::{self, sync_channel};
use libsupport_zynq::boot::Core1;
use super::{CHANNEL_0TO1, CHANNEL_1TO0, CHANNEL_SEM, INIT_LOCK, Message};
use crate::irq::restart_core1;
use core::mem::{forget, replace};
use super::{CHANNEL_0TO1, CHANNEL_1TO0, Message};
pub struct Control {
pub tx: Sender<'static, Message>,
pub rx: Receiver<'static, Message>,
}
fn get_channels() -> (Sender<'static, Message>, Receiver<'static, Message>) {
CHANNEL_SEM.wait();
let mut core0_tx = None;
while core0_tx.is_none() {
core0_tx = CHANNEL_0TO1.lock().take();
}
let core0_tx = core0_tx.unwrap();
let mut core0_rx = None;
while core0_rx.is_none() {
core0_rx = CHANNEL_1TO0.lock().take();
}
let core0_rx = core0_rx.unwrap();
(core0_tx, core0_rx)
core1: Core1,
pub tx: sync_channel::Sender<Message>,
pub rx: sync_channel::Receiver<Message>,
}
impl Control {
pub fn start() -> Self {
Core1::start(true);
let (core0_tx, core0_rx) = get_channels();
let core1 = Core1::start(true);
let (core0_tx, core1_rx) = sync_channel(4);
let (core1_tx, core0_rx) = sync_channel(4);
*CHANNEL_0TO1.lock() = Some(core1_rx);
*CHANNEL_1TO0.lock() = Some(core1_tx);
Control {
core1,
tx: core0_tx,
rx: core0_rx,
}
}
pub fn restart(&mut self) {
{
let _lock = INIT_LOCK.lock();
restart_core1();
unsafe {
self.tx.drop_elements();
}
}
let (core0_tx, core0_rx) = get_channels();
// dangling pointer here, so we forget it
forget(replace(&mut self.tx, core0_tx));
forget(replace(&mut self.rx, core0_rx));
*CHANNEL_0TO1.lock() = None;
*CHANNEL_1TO0.lock() = None;
self.core1.restart();
let (core0_tx, core1_rx) = sync_channel(4);
let (core1_tx, core0_rx) = sync_channel(4);
*CHANNEL_0TO1.lock() = Some(core1_rx);
*CHANNEL_1TO0.lock() = Some(core1_tx);
self.tx = core0_tx;
self.rx = core0_rx;
}
}

134
src/runtime/src/kernel/core1.rs
View File

@ -1,43 +1,23 @@
//! Kernel prologue/epilogue that runs on the 2nd CPU core
use core::{mem, ptr, cell::UnsafeCell};
use core::{mem, ptr};
use alloc::borrow::ToOwned;
use log::{debug, info, error};
use cslice::CSlice;
use libcortex_a9::{
enable_fpu,
cache::{dcci_slice, iciallu, bpiall},
asm::{dsb, isb},
sync_channel,
};
use libboard_zynq::{mpcore, gic};
use libsupport_zynq::ram;
use libcortex_a9::{enable_fpu, cache::dcci_slice, sync_channel};
use dyld::{self, Library};
use crate::{eh_artiq, rtio};
use crate::eh_artiq;
use super::{
api::resolve,
rpc::rpc_send_async,
INIT_LOCK,
CHANNEL_0TO1, CHANNEL_1TO0,
CHANNEL_SEM,
KERNEL_CHANNEL_0TO1, KERNEL_CHANNEL_1TO0,
KERNEL_IMAGE,
Message,
dma,
};
// linker symbols
extern "C" {
#[no_mangle]
static __text_start: u32;
#[no_mangle]
static __text_end: u32;
#[no_mangle]
static __exidx_start: u32;
#[no_mangle]
static __exidx_end: u32;
}
/// will contain the kernel image address on the heap
static mut KERNEL_LOAD_ADDR: usize = 0;
unsafe fn attribute_writeback(typeinfo: *const ()) {
struct Attr {
@ -78,8 +58,8 @@ unsafe fn attribute_writeback(typeinfo: *const ()) {
}
}
pub struct KernelImage {
library: UnsafeCell<Library>,
struct KernelImage {
library: Library,
__modinit__: u32,
typeinfo: Option<u32>,
}
@ -102,25 +82,16 @@ impl KernelImage {
}
Ok(KernelImage {
library: UnsafeCell::new(library),
library,
__modinit__,
typeinfo,
})
}
pub unsafe fn rebind(&self, name: &[u8], addr: *const ()) -> Result<(), dyld::Error> {
let library = self.library.get().as_mut().unwrap();
library.rebind(name, addr)
}
pub unsafe fn exec(&self) {
pub unsafe fn exec(&mut self) {
// Flush data cache entries for the image in DDR, including
// Memory/Instruction Synchronization Barriers
dcci_slice(self.library.get().as_ref().unwrap().image.data);
iciallu();
bpiall();
dsb();
isb();
// Memory/Instruction Symchronization Barriers
dcci_slice(self.library.image.data);
(mem::transmute::<u32, fn()>(self.__modinit__))();
@ -128,50 +99,40 @@ impl KernelImage {
attribute_writeback(typeinfo as *const ());
}
}
pub fn get_load_addr(&self) -> usize {
unsafe {
self.library.get().as_ref().unwrap().image.as_ptr() as usize
}
}
}
#[no_mangle]
pub fn main_core1() {
enable_fpu();
debug!("Core1 started");
ram::init_alloc_core1();
gic::InterruptController::gic(mpcore::RegisterBlock::mpcore()).enable_interrupts();
enable_fpu();
debug!("FPU enabled on Core1");
let (mut core0_tx, mut core1_rx) = sync_channel!(Message, 4);
let (mut core1_tx, core0_rx) = sync_channel!(Message, 4);
unsafe {
INIT_LOCK.lock();
core0_tx.reset();
core1_tx.reset();
if !KERNEL_IMAGE.is_null() {
// indicates forceful termination of previous kernel
KERNEL_IMAGE = core::ptr::null();
debug!("rtio init");
rtio::init();
}
dma::init_dma_recorder();
let mut core1_tx = None;
while core1_tx.is_none() {
core1_tx = CHANNEL_1TO0.lock().take();
}
*CHANNEL_0TO1.lock() = Some(core0_tx);
*CHANNEL_1TO0.lock() = Some(core0_rx);
CHANNEL_SEM.signal();
let mut core1_tx = core1_tx.unwrap();
let mut core1_rx = None;
while core1_rx.is_none() {
core1_rx = CHANNEL_0TO1.lock().take();
}
let mut core1_rx = core1_rx.unwrap();
// set on load, cleared on start
let mut loaded_kernel = None;
loop {
let message = core1_rx.recv();
match message {
match *message {
Message::LoadRequest(data) => {
let result = dyld::load(&data, &resolve)
.and_then(KernelImage::new);
match result {
Ok(kernel) => {
unsafe {
KERNEL_LOAD_ADDR = kernel.library.image.as_ptr() as usize;
}
loaded_kernel = Some(kernel);
debug!("kernel loaded");
core1_tx.send(Message::LoadCompleted);
@ -184,15 +145,13 @@ pub fn main_core1() {
},
Message::StartRequest => {
info!("kernel starting");
if let Some(kernel) = loaded_kernel.take() {
if let Some(mut kernel) = loaded_kernel.take() {
unsafe {
KERNEL_CHANNEL_0TO1 = Some(core1_rx);
KERNEL_CHANNEL_1TO0 = Some(core1_tx);
KERNEL_IMAGE = &kernel as *const KernelImage;
KERNEL_CHANNEL_0TO1 = mem::transmute(&mut core1_rx);
KERNEL_CHANNEL_1TO0 = mem::transmute(&mut core1_tx);
kernel.exec();
KERNEL_IMAGE = ptr::null();
core1_rx = KERNEL_CHANNEL_0TO1.take().unwrap();
core1_tx = KERNEL_CHANNEL_1TO0.take().unwrap();
KERNEL_CHANNEL_0TO1 = ptr::null_mut();
KERNEL_CHANNEL_1TO0 = ptr::null_mut();
}
}
info!("kernel finished");
@ -206,7 +165,7 @@ pub fn main_core1() {
/// Called by eh_artiq
pub fn terminate(exception: &'static eh_artiq::Exception<'static>, backtrace: &'static mut [usize]) -> ! {
let load_addr = unsafe {
KERNEL_IMAGE.as_ref().unwrap().get_load_addr()
KERNEL_LOAD_ADDR
};
let mut cursor = 0;
// The address in the backtrace is relocated, so we have to convert it back to the address in
@ -218,30 +177,7 @@ pub fn terminate(exception: &'static eh_artiq::Exception<'static>, backtrace: &'
}
}
{
let core1_tx = unsafe { KERNEL_CHANNEL_1TO0.as_mut().unwrap() };
core1_tx.send(Message::KernelException(exception, &backtrace[..cursor]));
}
let core1_tx: &mut sync_channel::Sender<Message> = unsafe { mem::transmute(KERNEL_CHANNEL_1TO0) };
core1_tx.send(Message::KernelException(exception, &backtrace[..cursor]));
loop {}
}
/// Called by llvm_libunwind
#[no_mangle]
extern fn dl_unwind_find_exidx(pc: *const u32, len_ptr: *mut u32) -> *const u32 {
let length;
let start: *const u32;
unsafe {
if &__text_start as *const u32 <= pc && pc < &__text_end as *const u32 {
length = (&__exidx_end as *const u32).offset_from(&__exidx_start) as u32;
start = &__exidx_start;
} else {
let exidx = KERNEL_IMAGE.as_ref()
.expect("dl_unwind_find_exidx kernel image")
.library.get().as_ref().unwrap().exidx();
length = exidx.len() as u32;
start = exidx.as_ptr();
}
*len_ptr = length;
}
start
}

212
src/runtime/src/kernel/dma.rs
View File

@ -1,212 +0,0 @@
use crate::{
pl::csr,
artiq_raise,
rtio,
};
use alloc::{vec::Vec, string::String, boxed::Box};
use cslice::CSlice;
use super::{KERNEL_IMAGE, KERNEL_CHANNEL_0TO1, KERNEL_CHANNEL_1TO0, Message};
use core::mem;
use libcortex_a9::cache::dcci_slice;
const ALIGNMENT: usize = 16 * 8;
#[repr(C)]
pub struct DmaTrace {
duration: i64,
address: i32,
}
#[derive(Clone, Debug)]
pub struct DmaRecorder {
pub name: String,
pub buffer: Vec<u8>,
pub duration: i64,
}
static mut RECORDER: Option<DmaRecorder> = None;
pub unsafe fn init_dma_recorder() {
// as static would remain after restart, we have to reset it,
// without running its destructor.
mem::forget(mem::replace(&mut RECORDER, None));
}
pub extern fn dma_record_start(name: CSlice<u8>) {
let name = String::from_utf8(name.as_ref().to_vec()).unwrap();
unsafe {
KERNEL_CHANNEL_1TO0.as_mut().unwrap().send(Message::DmaEraseRequest(name.clone()));
}
unsafe {
if RECORDER.is_some() {
artiq_raise!("DMAError", "DMA is already recording")
}
let library = KERNEL_IMAGE.as_ref().unwrap();
library.rebind(b"rtio_output",
dma_record_output as *const ()).unwrap();
library.rebind(b"rtio_output_wide",
dma_record_output_wide as *const ()).unwrap();
RECORDER = Some(DmaRecorder {
name,
buffer: Vec::new(),
duration: 0,
});
}
}
pub extern fn dma_record_stop(duration: i64) {
unsafe {
if RECORDER.is_none() {
artiq_raise!("DMAError", "DMA is not recording")
}
let library = KERNEL_IMAGE.as_ref().unwrap();
library.rebind(b"rtio_output",
rtio::output as *const ()).unwrap();
library.rebind(b"rtio_output_wide",
rtio::output_wide as *const ()).unwrap();
let mut recorder = RECORDER.take().unwrap();
recorder.duration = duration;
KERNEL_CHANNEL_1TO0.as_mut().unwrap().send(
Message::DmaPutRequest(recorder)
);
}
}
#[inline(always)]
unsafe fn dma_record_output_prepare(timestamp: i64, target: i32,
words: usize) {
// See gateware/rtio/dma.py.
const HEADER_LENGTH: usize = /*length*/1 + /*channel*/3 + /*timestamp*/8 + /*address*/1;
let length = HEADER_LENGTH + /*data*/words * 4;
let buffer = &mut RECORDER.as_mut().unwrap().buffer;
buffer.reserve(length);
buffer.extend_from_slice(&[
(length >> 0) as u8,
(target >> 8) as u8,
(target >> 16) as u8,
(target >> 24) as u8,
(timestamp >> 0) as u8,
(timestamp >> 8) as u8,
(timestamp >> 16) as u8,
(timestamp >> 24) as u8,
(timestamp >> 32) as u8,
(timestamp >> 40) as u8,
(timestamp >> 48) as u8,
(timestamp >> 56) as u8,
(target >> 0) as u8,
]);
}
pub extern fn dma_record_output(target: i32, word: i32) {
unsafe {
let timestamp = rtio::now_mu();
dma_record_output_prepare(timestamp, target, 1);
RECORDER.as_mut().unwrap().buffer.extend_from_slice(&[
(word >> 0) as u8,
(word >> 8) as u8,
(word >> 16) as u8,
(word >> 24) as u8,
]);
}
}
pub extern fn dma_record_output_wide(target: i32, words: CSlice<i32>) {
assert!(words.len() <= 16); // enforce the hardware limit
unsafe {
let timestamp = rtio::now_mu();
dma_record_output_prepare(timestamp, target, words.len());
let buffer = &mut RECORDER.as_mut().unwrap().buffer;
for word in words.as_ref().iter() {
buffer.extend_from_slice(&[
(word >> 0) as u8,
(word >> 8) as u8,
(word >> 16) as u8,
(word >> 24) as u8,
]);
}
}
}
pub extern fn dma_erase(name: CSlice<u8>) {
let name = String::from_utf8(name.as_ref().to_vec()).unwrap();
unsafe {
KERNEL_CHANNEL_1TO0.as_mut().unwrap().send(Message::DmaEraseRequest(name));
}
}
pub extern fn dma_retrieve(name: CSlice<u8>) -> DmaTrace {
let name = String::from_utf8(name.as_ref().to_vec()).unwrap();
unsafe {
KERNEL_CHANNEL_1TO0.as_mut().unwrap().send(Message::DmaGetRequest(name));
}
match unsafe {KERNEL_CHANNEL_0TO1.as_mut().unwrap()}.recv() {
Message::DmaGetReply(None) => (),
Message::DmaGetReply(Some((mut v, duration))) => {
v.reserve(ALIGNMENT - 1);
let original_length = v.len();
let padding = ALIGNMENT - v.as_ptr() as usize % ALIGNMENT;
let padding = if padding == ALIGNMENT { 0 } else { padding };
for _ in 0..padding {
v.push(0);
}
// trailing zero to indicate end of buffer
v.push(0);
v.copy_within(0..original_length, padding);
dcci_slice(&v);
let v = Box::new(v);
let address = Box::into_raw(v) as *mut Vec<u8> as i32;
return DmaTrace {
address,
duration,
};
},
_ => panic!("Expected DmaGetReply after DmaGetRequest!"),
}
// we have to defer raising error as we have to drop the message first...
artiq_raise!("DMAError", "DMA trace not found");
}
pub extern fn dma_playback(timestamp: i64, ptr: i32) {
unsafe {
let v = Box::from_raw(ptr as *mut Vec<u8>);
let padding = ALIGNMENT - v.as_ptr() as usize % ALIGNMENT;
let padding = if padding == ALIGNMENT { 0 } else { padding };
let ptr = v.as_ptr().add(padding) as i32;
csr::rtio_dma::base_address_write(ptr as u32);
csr::rtio_dma::time_offset_write(timestamp as u64);
csr::cri_con::selected_write(1);
csr::rtio_dma::enable_write(1);
while csr::rtio_dma::enable_read() != 0 {}
csr::cri_con::selected_write(0);
// leave the handle as we may try to do playback for another time.
mem::forget(v);
let error = csr::rtio_dma::error_read();
if error != 0 {
let timestamp = csr::rtio_dma::error_timestamp_read();
let channel = csr::rtio_dma::error_channel_read();
csr::rtio_dma::error_write(1);
if error & 1 != 0 {
artiq_raise!("RTIOUnderflow",
"RTIO underflow at {0} mu, channel {1}",
timestamp as i64, channel as i64, 0);
}
if error & 2 != 0 {
artiq_raise!("RTIODestinationUnreachable",
"RTIO destination unreachable, output, at {0} mu, channel {1}",
timestamp as i64, channel as i64, 0);
}
}
}
}

38
src/runtime/src/kernel/mod.rs
View File

@ -1,7 +1,7 @@
use core::ptr;
use alloc::{vec::Vec, string::String};
use alloc::{vec::Vec, sync::Arc, string::String};
use libcortex_a9::{mutex::Mutex, sync_channel, semaphore::Semaphore};
use libcortex_a9::{mutex::Mutex, sync_channel};
use crate::eh_artiq;
mod control;
@ -9,11 +9,8 @@ pub use control::Control;
pub mod core1;
mod api;
mod rpc;
mod dma;
pub use dma::DmaRecorder;
mod cache;
#[derive(Debug, Clone)]
#[derive(Debug)]
pub struct RPCException {
pub name: String,
pub message: String,
@ -24,36 +21,21 @@ pub struct RPCException {
pub function: String
}
#[derive(Debug, Clone)]
#[derive(Debug)]
pub enum Message {
LoadRequest(Vec<u8>),
LoadRequest(Arc<Vec<u8>>),
LoadCompleted,
LoadFailed,
StartRequest,
KernelFinished,
KernelException(&'static eh_artiq::Exception<'static>, &'static [usize]),
RpcSend { is_async: bool, data: Vec<u8> },
RpcSend { is_async: bool, data: Arc<Vec<u8>> },
RpcRecvRequest(*mut ()),
RpcRecvReply(Result<usize, RPCException>),
CacheGetRequest(String),
CacheGetReply(Vec<i32>),
CachePutRequest(String, Vec<i32>),
DmaPutRequest(DmaRecorder),
DmaEraseRequest(String),
DmaGetRequest(String),
DmaGetReply(Option<(Vec<u8>, i64)>),
}
static CHANNEL_0TO1: Mutex<Option<sync_channel::Sender<'static, Message>>> = Mutex::new(None);
static CHANNEL_1TO0: Mutex<Option<sync_channel::Receiver<'static, Message>>> = Mutex::new(None);
static CHANNEL_SEM: Semaphore = Semaphore::new(0, 1);
static mut KERNEL_CHANNEL_0TO1: Option<sync_channel::Receiver<'static, Message>> = None;
static mut KERNEL_CHANNEL_1TO0: Option<sync_channel::Sender<'static, Message>> = None;
static mut KERNEL_IMAGE: *const core1::KernelImage = ptr::null();
static INIT_LOCK: Mutex<()> = Mutex::new(());
static CHANNEL_0TO1: Mutex<Option<sync_channel::Receiver<Message>>> = Mutex::new(None);
static CHANNEL_1TO0: Mutex<Option<sync_channel::Sender<Message>>> = Mutex::new(None);
static mut KERNEL_CHANNEL_0TO1: *mut () = ptr::null_mut();
static mut KERNEL_CHANNEL_1TO0: *mut () = ptr::null_mut();

20
src/runtime/src/kernel/rpc.rs
View File

@ -1,8 +1,10 @@
//! Kernel-side RPC API
use alloc::vec::Vec;
use core::mem;
use alloc::{vec::Vec, sync::Arc};
use cslice::{CSlice, AsCSlice};
use libcortex_a9::sync_channel;
use crate::eh_artiq;
use crate::rpc::send_args;
use super::{
@ -11,10 +13,10 @@ use super::{
};
fn rpc_send_common(is_async: bool, service: u32, tag: &CSlice<u8>, data: *const *const ()) {
let core1_tx = unsafe { KERNEL_CHANNEL_1TO0.as_mut().unwrap() };
let core1_tx: &mut sync_channel::Sender<Message> = unsafe { mem::transmute(KERNEL_CHANNEL_1TO0) };
let mut buffer = Vec::<u8>::new();
send_args(&mut buffer, service, tag.as_ref(), data).expect("RPC encoding failed");
core1_tx.send(Message::RpcSend { is_async, data: buffer });
core1_tx.send(Message::RpcSend { is_async: is_async, data: Arc::new(buffer) });
}
pub extern fn rpc_send(service: u32, tag: &CSlice<u8>, data: *const *const ()) {
@ -26,13 +28,11 @@ pub extern fn rpc_send_async(service: u32, tag: &CSlice<u8>, data: *const *const
}
pub extern fn rpc_recv(slot: *mut ()) -> usize {
let reply = unsafe {
let core1_rx = KERNEL_CHANNEL_0TO1.as_mut().unwrap();
let core1_tx = KERNEL_CHANNEL_1TO0.as_mut().unwrap();
core1_tx.send(Message::RpcRecvRequest(slot));
core1_rx.recv()
};
match reply {
let core1_rx: &mut sync_channel::Receiver<Message> = unsafe { mem::transmute(KERNEL_CHANNEL_0TO1) };
let core1_tx: &mut sync_channel::Sender<Message> = unsafe { mem::transmute(KERNEL_CHANNEL_1TO0) };
core1_tx.send(Message::RpcRecvRequest(slot));
let reply = core1_rx.recv();
match *reply {
Message::RpcRecvReply(Ok(alloc_size)) => alloc_size,
Message::RpcRecvReply(Err(exception)) => unsafe {
eh_artiq::raise(&eh_artiq::Exception {

171
src/runtime/src/load_pl.rs Normal file
View File

@ -0,0 +1,171 @@
use crate::sd_reader;
use core_io::{Error, Read, Seek, SeekFrom};
use libboard_zynq::{devc, sdio};
use log::{info, debug};
#[derive(Debug)]
pub enum PlLoadingError {
BootImageNotFound,
InvalidBootImageHeader,
MissingBitstreamPartition,
EncryptedBitstream,
IoError(Error),
DevcError(devc::DevcError),
}
impl From<Error> for PlLoadingError {
fn from(error: Error) -> Self {
PlLoadingError::IoError(error)
}
}
impl From<devc::DevcError> for PlLoadingError {
fn from(error: devc::DevcError) -> Self {
PlLoadingError::DevcError(error)
}
}
impl core::fmt::Display for PlLoadingError {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
use PlLoadingError::*;
match self {
BootImageNotFound => write!(
f,
"Boot image not found, make sure `boot.bin` exists and your SD card is plugged in."
),
InvalidBootImageHeader => write!(
f,
"Invalid boot image header. Check if the file is correct."
),
MissingBitstreamPartition => write!(
f,
"Bitstream partition not found. Check your compile configuration."
),
EncryptedBitstream => write!(f, "Encrypted bitstream is not supported."),
IoError(e) => write!(f, "Error while reading: {}", e),
DevcError(e) => write!(f, "PCAP interface error: {}", e),
}
}
}
#[repr(C)]
struct PartitionHeader {
pub encrypted_length: u32,
pub unencrypted_length: u32,
pub word_length: u32,
pub dest_load_addr: u32,
pub dest_exec_addr: u32,
pub data_offset: u32,
pub attribute_bits: u32,
pub section_count: u32,
pub checksum_offset: u32,
pub header_offset: u32,
pub cert_offset: u32,
pub reserved: [u32; 4],
pub checksum: u32,
}
/// Read a u32 word from the reader.
fn read_u32<Reader: Read>(reader: &mut Reader) -> Result<u32, PlLoadingError> {
let mut buffer: [u8; 4] = [0; 4];
reader.read_exact(&mut buffer)?;
let mut result: u32 = 0;
for i in 0..4 {
result |= (buffer[i] as u32) << (i * 8);
}
Ok(result)
}
/// Load PL partition header.
fn load_pl_header<File: Read + Seek>(
file: &mut File,
) -> Result<Option<PartitionHeader>, PlLoadingError> {
let mut buffer: [u8; 0x40] = [0; 0x40];
file.read_exact(&mut buffer)?;
let header = unsafe { core::mem::transmute::<_, PartitionHeader>(buffer) };
if header.attribute_bits & (2 << 4) != 0 {
Ok(Some(header))
} else {
Ok(None)
}
}
/// Locate the PL bitstream from the image, and return the size (in bytes) of the bitstream if successful.
/// This function would seek the file to the location of the bitstream.
fn locate_bitstream<File: Read + Seek>(file: &mut File) -> Result<usize, PlLoadingError> {
const BOOT_HEADER_SIGN: u32 = 0x584C4E58;
// read boot header signature
file.seek(SeekFrom::Start(0x24))?;
if read_u32(file)? != BOOT_HEADER_SIGN {
return Err(PlLoadingError::InvalidBootImageHeader);
}
// read partition header offset
file.seek(SeekFrom::Start(0x9C))?;
let ptr = read_u32(file)?;
debug!("Partition header pointer = {:0X}", ptr);
file.seek(SeekFrom::Start(ptr as u64))?;
let mut header_opt = None;
// at most 3 partition headers
for _ in 0..3 {
let result = load_pl_header(file)?;
if let Some(h) = result {
header_opt = Some(h);
break;
}
}
let header = match header_opt {
None => return Err(PlLoadingError::MissingBitstreamPartition),
Some(h) => h,
};
let encrypted_length = header.encrypted_length;
let unencrypted_length = header.unencrypted_length;
debug!("Unencrypted length = {:0X}", unencrypted_length);
if encrypted_length != unencrypted_length {
return Err(PlLoadingError::EncryptedBitstream);
}
let start_addr = header.data_offset;
debug!("Partition start address: {:0X}", start_addr);
file.seek(SeekFrom::Start(start_addr as u64 * 4))?;
Ok(unencrypted_length as usize * 4)
}
/// Load bitstream from bootgen file.
/// This function parses the file, locate the bitstream and load it through the PCAP driver.
/// It requires a large buffer, please enable the DDR RAM before using it.
pub fn load_bitstream<File: Read + Seek>(
file: &mut File,
) -> Result<(), PlLoadingError> {
let size = locate_bitstream(file)?;
let mut buffer: alloc::vec::Vec<u8> = alloc::vec::Vec::with_capacity(size);
unsafe {
buffer.set_len(buffer.capacity());
}
file.read_exact(&mut buffer)?;
let mut devcfg = devc::DevC::new();
devcfg.enable();
devcfg.program(&buffer)?;
Ok(())
}
pub fn load_bitstream_from_sd() -> Result<(), PlLoadingError> {
let sdio0 = sdio::SDIO::sdio0(true);
if sdio0.is_card_inserted() {
info!("Card inserted. Mounting file system.");
let sd = sdio::sd_card::SdCard::from_sdio(sdio0).unwrap();
let reader = sd_reader::SdReader::new(sd);
let fs = reader.mount_fatfs(sd_reader::PartitionEntry::Entry1)?;
let root_dir = fs.root_dir();
let mut file = root_dir.open_file("/BOOT.BIN").map_err(|_| PlLoadingError::BootImageNotFound)?;
info!("Found boot image!");
load_bitstream(&mut file)
} else {
info!("SD card not inserted. Bitstream cannot be loaded.");
Err(PlLoadingError::BootImageNotFound)
}
}

44
src/runtime/src/logger.rs
View File

@ -1,17 +1,16 @@
use core::cell::Cell;
use core::cell::{Cell, RefCell, RefMut};
use core::fmt::Write;
use log::{Log, LevelFilter};
use log_buffer::LogBuffer;
use libcortex_a9::mutex::{Mutex, MutexGuard};
use libboard_zynq::{println, timer::GlobalTimer};
pub struct LogBufferRef<'a> {
buffer: MutexGuard<'a, LogBuffer<&'static mut [u8]>>,
buffer: RefMut<'a, LogBuffer<&'static mut [u8]>>,
old_log_level: LevelFilter
}
impl<'a> LogBufferRef<'a> {
fn new(buffer: MutexGuard<'a, LogBuffer<&'static mut [u8]>>) -> LogBufferRef<'a> {
fn new(buffer: RefMut<'a, LogBuffer<&'static mut [u8]>>) -> LogBufferRef<'a> {
let old_log_level = log::max_level();
log::set_max_level(LevelFilter::Off);
LogBufferRef { buffer, old_log_level }
@ -37,9 +36,8 @@ impl<'a> Drop for LogBufferRef<'a> {
}
pub struct BufferLogger {
buffer: Mutex<LogBuffer<&'static mut [u8]>>,
uart_filter: Cell<LevelFilter>,
buffer_filter: Cell<LevelFilter>,
buffer: RefCell<LogBuffer<&'static mut [u8]>>,
uart_filter: Cell<LevelFilter>
}
static mut LOGGER: Option<BufferLogger> = None;
@ -47,28 +45,30 @@ static mut LOGGER: Option<BufferLogger> = None;
impl BufferLogger {
pub fn new(buffer: &'static mut [u8]) -> BufferLogger {
BufferLogger {
buffer: Mutex::new(LogBuffer::new(buffer)),
buffer: RefCell::new(LogBuffer::new(buffer)),
uart_filter: Cell::new(LevelFilter::Info),
buffer_filter: Cell::new(LevelFilter::Trace),
}
}
pub fn register(self) {
pub fn register<F: FnOnce()>(self, f: F) {
unsafe {
LOGGER = Some(self);
log::set_logger(LOGGER.as_ref().unwrap())
.expect("global logger can only be initialized once");
}
log::set_max_level(LevelFilter::Info);
f();
}
pub unsafe fn get_logger() -> &'static mut Option<BufferLogger> {
&mut LOGGER
pub fn with<R, F: FnOnce(&BufferLogger) -> R>(f: F) -> R {
f(unsafe { LOGGER.as_ref().expect("with logger") })
}
pub fn buffer<'a>(&'a self) -> Option<LogBufferRef<'a>> {
pub fn buffer<'a>(&'a self) -> Result<LogBufferRef<'a>, ()> {
self.buffer
.try_lock()
.try_borrow_mut()
.map(LogBufferRef::new)
.map_err(|_| ())
}
pub fn uart_log_level(&self) -> LevelFilter {
@ -78,15 +78,6 @@ impl BufferLogger {
pub fn set_uart_log_level(&self, max_level: LevelFilter) {
self.uart_filter.set(max_level)
}
pub fn buffer_log_level(&self) -> LevelFilter {
self.buffer_filter.get()
}
/// this should be reserved for mgmt module
pub fn set_buffer_log_level(&self, max_level: LevelFilter) {
self.buffer_filter.set(max_level)
}
}
// required for impl Log
@ -101,17 +92,16 @@ impl Log for BufferLogger {
if self.enabled(record.metadata()) {
let timestamp = unsafe {
GlobalTimer::get()
}.get_us().0;
}.get_us();
let seconds = timestamp / 1_000_000;
let micros = timestamp % 1_000_000;
if record.level() <= self.buffer_log_level() {
let mut buffer = self.buffer.lock();
if let Ok(mut buffer) = self.buffer.try_borrow_mut() {
writeln!(buffer, "[{:6}.{:06}s] {:>5}({}): {}", seconds, micros,
record.level(), record.target(), record.args()).unwrap();
}
if record.level() <= self.uart_log_level() {
if record.level() <= self.uart_filter.get() {
println!("[{:6}.{:06}s] {:>5}({}): {}", seconds, micros,
record.level(), record.target(), record.args());
}

133
src/runtime/src/main.rs
View File

@ -3,47 +3,34 @@
#![recursion_limit="1024"] // for futures_util::select!
#![feature(alloc_error_handler)]
#![feature(panic_info_message)]
#![feature(c_variadic)]
#![feature(const_btree_new)]
#![feature(ptr_offset_from)]
#![feature(const_in_array_repeat_expressions)]
#![feature(naked_functions)]
extern crate alloc;
use core::{cmp, str};
use log::{info, warn, error};
use log::{info, warn};
use libboard_zynq::{timer::GlobalTimer, mpcore, gic, slcr};
use libasync::{task, block_async};
use libboard_zynq::{timer::GlobalTimer, time::Milliseconds, devc, slcr, println};
use libsupport_zynq::ram;
use nb;
use void::Void;
use embedded_hal::blocking::delay::DelayMs;
use libconfig::Config;
use libregister::RegisterW;
use nb::block;
use embedded_hal::timer::CountDown;
mod sd_reader;
mod config;
mod net_settings;
mod proto_core_io;
mod proto_async;
mod comms;
mod rpc;
#[path = "../../../build/pl.rs"]
mod pl;
#[cfg(ki_impl = "csr")]
#[path = "rtio_csr.rs"]
mod rtio;
#[cfg(ki_impl = "acp")]
#[path = "rtio_acp.rs"]
mod rtio;
mod kernel;
mod moninj;
mod load_pl;
mod eh_artiq;
mod panic;
mod logger;
mod mgmt;
mod analyzer;
mod irq;
mod i2c;
fn init_gateware() {
// Set up PS->PL clocks
@ -66,6 +53,22 @@ fn init_gateware() {
slcr::FpgaRstCtrl::zeroed()
);
});
if devc::DevC::new().is_done() {
info!("gateware already loaded");
// Do not load again: assume that the gateware already present is
// what we want (e.g. gateware configured via JTAG before PS
// startup, or by FSBL).
// Make sure that the PL/PS interface is enabled (e.g. OpenOCD does not enable it).
slcr::RegisterBlock::unlocked(|slcr| {
slcr.init_postload_fpga();
});
} else {
// Load from SD card
match load_pl::load_bitstream_from_sd() {
Ok(_) => info!("Bitstream loaded successfully!"),
Err(e) => info!("Failure loading bitstream: {}", e),
}
}
}
fn identifier_read(buf: &mut [u8]) -> &str {
@ -81,7 +84,7 @@ fn identifier_read(buf: &mut [u8]) -> &str {
}
}
fn init_rtio(timer: &mut GlobalTimer, cfg: &Config) {
fn init_rtio(timer: GlobalTimer, cfg: &config::Config) {
let clock_sel =
if let Ok(rtioclk) = cfg.read_str("rtioclk") {
match rtioclk.as_ref() {
@ -104,21 +107,17 @@ fn init_rtio(timer: &mut GlobalTimer, cfg: &Config) {
0
};
loop {
unsafe {
pl::csr::rtio_crg::pll_reset_write(1);
pl::csr::rtio_crg::clock_sel_write(clock_sel);
pl::csr::rtio_crg::pll_reset_write(0);
}
timer.delay_ms(1);
let locked = unsafe { pl::csr::rtio_crg::pll_locked_read() != 0 };
if locked {
info!("RTIO PLL locked");
break;
} else {
warn!("RTIO PLL failed to lock, retrying...");
timer.delay_ms(500);
}
unsafe {
pl::csr::rtio_crg::pll_reset_write(1);
pl::csr::rtio_crg::clock_sel_write(clock_sel);
pl::csr::rtio_crg::pll_reset_write(0);
}
let mut countdown = timer.countdown();
countdown.start(Milliseconds(1));
block!(countdown.wait()).unwrap();
let locked = unsafe { pl::csr::rtio_crg::pll_locked_read() != 0 };
if !locked {
panic!("RTIO PLL failed to lock");
}
unsafe {
@ -126,71 +125,33 @@ fn init_rtio(timer: &mut GlobalTimer, cfg: &Config) {
}
}
fn wait_for_async_rtio_error() -> nb::Result<(), Void> {
unsafe {
if pl::csr::rtio_core::async_error_read() != 0 {
Ok(())
} else {
Err(nb::Error::WouldBlock)
}
}
}
async fn report_async_rtio_errors() {
loop {
let _ = block_async!(wait_for_async_rtio_error()).await;
unsafe {
let errors = pl::csr::rtio_core::async_error_read();
if errors & 1 != 0 {
error!("RTIO collision involving channel {}",
pl::csr::rtio_core::collision_channel_read());
}
if errors & 2 != 0 {
error!("RTIO busy error involving channel {}",
pl::csr::rtio_core::busy_channel_read());
}
if errors & 4 != 0 {
error!("RTIO sequence error involving channel {}",
pl::csr::rtio_core::sequence_error_channel_read());
}
pl::csr::rtio_core::async_error_write(errors);
}
}
}
static mut LOG_BUFFER: [u8; 1<<17] = [0; 1<<17];
#[no_mangle]
pub fn main_core0() {
let mut timer = GlobalTimer::start();
let buffer_logger = unsafe {
logger::BufferLogger::new(&mut LOG_BUFFER[..])
};
buffer_logger.set_uart_log_level(log::LevelFilter::Info);
buffer_logger.register();
log::set_max_level(log::LevelFilter::Info);
let timer = GlobalTimer::start();
unsafe {
println!("BUFFER ADDR = {:p}", LOG_BUFFER.as_ptr());
println!("BUFFER LEN = {}", LOG_BUFFER.len());
logger::BufferLogger::new(&mut LOG_BUFFER[..]).register(|| {});
}
log::set_max_level(log::LevelFilter::Debug);
info!("NAR3/Zynq7000 starting...");
ram::init_alloc_core0();
gic::InterruptController::gic(mpcore::RegisterBlock::mpcore()).enable_interrupts();
ram::init_alloc_linker();
init_gateware();
info!("detected gateware: {}", identifier_read(&mut [0; 64]));
i2c::init();
let cfg = match Config::new() {
let cfg = match config::Config::new() {
Ok(cfg) => cfg,
Err(err) => {
warn!("config initialization failed: {}", err);
Config::new_dummy()
config::Config::new_dummy()
}
};
init_rtio(&mut timer, &cfg);
task::spawn(report_async_rtio_errors());
init_rtio(timer, &cfg);
comms::main(timer, &cfg);
}

217
src/runtime/src/mgmt.rs
View File

@ -1,217 +0,0 @@
use futures::{future::poll_fn, task::Poll};
use libasync::{smoltcp::TcpStream, task};
use libboard_zynq::smoltcp;
use libconfig::Config;
use core::{cell::RefCell, convert::TryInto};
use alloc::{vec::Vec, rc::Rc, str, string::String};
use log::{self, info, warn, LevelFilter};
use crate::logger::{BufferLogger, LogBufferRef};
use crate::proto_async::*;
use num_derive::FromPrimitive;
use num_traits::FromPrimitive;
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Error {
NetworkError(smoltcp::Error),
UnknownLogLevel(u8),
UnexpectedPattern,
UnrecognizedPacket,
}
type Result<T> = core::result::Result<T, Error>;
impl core::fmt::Display for Error {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
match self {
&Error::NetworkError(error) => write!(f, "network error: {}", error),
&Error::UnknownLogLevel(lvl) => write!(f, "unknown log level {}", lvl),
&Error::UnexpectedPattern => write!(f, "unexpected pattern"),
&Error::UnrecognizedPacket => write!(f, "unrecognized packet"),
}
}
}
impl From<smoltcp::Error> for Error {
fn from(error: smoltcp::Error) -> Self {
Error::NetworkError(error)
}
}
#[derive(Debug, FromPrimitive)]
pub enum Request {
GetLog = 1,
ClearLog = 2,
PullLog = 7,
SetLogFilter = 3,
SetUartLogFilter = 6,
ConfigRead = 12,
ConfigWrite = 13,
ConfigRemove = 14,
ConfigErase = 15,
}
#[repr(i8)]
pub enum Reply {
Success = 1,
LogContent = 2,
ConfigData = 7,
}
async fn read_log_level_filter(stream: &mut TcpStream) -> Result<log::LevelFilter> {
Ok(match read_i8(stream).await? {
0 => log::LevelFilter::Off,
1 => log::LevelFilter::Error,
2 => log::LevelFilter::Warn,
3 => log::LevelFilter::Info,
4 => log::LevelFilter::Debug,
5 => log::LevelFilter::Trace,
lv => return Err(Error::UnknownLogLevel(lv as u8)),
})
}
async fn get_logger_buffer_pred<F>(f: F) -> LogBufferRef<'static>
where
F: Fn(&LogBufferRef) -> bool,
{
poll_fn(|ctx| {
let logger = unsafe { BufferLogger::get_logger().as_mut().unwrap() };
match logger.buffer() {
Some(buffer) if f(&buffer) => Poll::Ready(buffer),
_ => {
ctx.waker().wake_by_ref();
Poll::Pending
}
}
})
.await
}
async fn get_logger_buffer() -> LogBufferRef<'static> {
get_logger_buffer_pred(|_| true).await
}
async fn get_config_bytes<'a>(stream: &mut TcpStream) -> Result<Vec<u8>> {
let len :i32 = read_i32(stream).await.unwrap();
let mut buffer: Vec<u8> = Vec::with_capacity(len.try_into().unwrap());
read_chunk(stream, &mut buffer).await;
return Ok(buffer);
}
async fn get_config_key<'a>(stream: &mut TcpStream) -> Result<String> {
Ok(String::from_utf8(get_config_bytes(stream).await?).unwrap())
}
async fn handle_connection(stream: &mut TcpStream, pull_id: Rc<RefCell<u32>>, cfg: Config) -> Result<()> {
if !expect(&stream, b"ARTIQ management\n").await? {
return Err(Error::UnexpectedPattern);
}
loop {
let msg = read_i8(stream).await;
if let Err(smoltcp::Error::Illegal) = msg {
return Ok(());
}
let msg: Request = FromPrimitive::from_i8(msg?).ok_or(Error::UnrecognizedPacket)?;
match msg {
Request::GetLog => {
let buffer = get_logger_buffer().await.extract().as_bytes().to_vec();
write_i8(stream, Reply::LogContent as i8).await?;
write_chunk(stream, &buffer).await?;
}
Request::ClearLog => {
let mut buffer = get_logger_buffer().await;
buffer.clear();
write_i8(stream, Reply::Success as i8).await?;
}
Request::PullLog => {
let id = {
let mut guard = pull_id.borrow_mut();
*guard += 1;
*guard
};
loop {
let mut buffer = get_logger_buffer_pred(|b| !b.is_empty()).await;
if id != *pull_id.borrow() {
// another connection attempts to pull the log...
// abort this connection...
break;
}
let bytes = buffer.extract().as_bytes().to_vec();
buffer.clear();
core::mem::drop(buffer);
write_chunk(stream, &bytes).await?;
if log::max_level() == LevelFilter::Trace {
// temporarily discard all trace level log
let logger = unsafe { BufferLogger::get_logger().as_mut().unwrap() };
logger.set_buffer_log_level(LevelFilter::Debug);
stream.flush().await?;
logger.set_buffer_log_level(LevelFilter::Trace);
}
}
},
Request::SetLogFilter => {
let lvl = read_log_level_filter(stream).await?;
info!("Changing log level to {}", lvl);
log::set_max_level(lvl);
write_i8(stream, Reply::Success as i8).await?;
}
Request::SetUartLogFilter => {
let lvl = read_log_level_filter(stream).await?;
info!("Changing UART log level to {}", lvl);
unsafe {
BufferLogger::get_logger()
.as_ref()
.unwrap()
.set_uart_log_level(lvl);
}
write_i8(stream, Reply::Success as i8).await?;
}
Request::ConfigRead => {
let key: &str = &*(get_config_key(stream).await.unwrap());
let data: Vec<u8> = cfg.read(key).unwrap();
write_i8(stream, Reply::ConfigData as i8).await?;
write_chunk(stream, &data).await?;
}
Request::ConfigWrite => {
let key: &str = &*(get_config_key(stream).await.unwrap());
let value: Vec<u8> = get_config_bytes(stream).await?;
cfg.write_str(key, str::from_utf8(&value).unwrap())?;
write_i8(stream, Reply::Success as i8).await?;
}
Request::ConfigRemove => {
let key: &str = &*(get_config_key(stream).await.unwrap());
cfg.remove(key)?;
write_i8(stream, Reply::Success as i8).await?;
}
Request::ConfigErase => {
cfg.erase()?;
write_i8(stream, Reply::Success as i8).await?;
}
}
}
}
pub fn start(cfg: Config) {
task::spawn(async move {
let pull_id = Rc::new(RefCell::new(0u32));
loop {
let mut stream = TcpStream::accept(1380, 2048, 2048).await.unwrap();
let pull_id = pull_id.clone();
task::spawn(async move {
info!("received connection");
let _ = handle_connection(&mut stream, pull_id, cfg)
.await
.map_err(|e| warn!("connection terminated: {:?}", e));
let _ = stream.flush().await;
let _ = stream.abort().await;
});
}
});
}

12
src/runtime/src/moninj.rs
View File

@ -1,6 +1,6 @@
use core::fmt;
use alloc::collections::BTreeMap;
use log::{debug, info, warn};
use log::{debug, warn};
use void::Void;
use libboard_zynq::{smoltcp, timer::GlobalTimer, time::Milliseconds};
@ -180,13 +180,9 @@ pub fn start(timer: GlobalTimer) {
loop {
let stream = TcpStream::accept(1383, 2048, 2048).await.unwrap();
task::spawn(async move {
info!("received connection");
let result = handle_connection(&stream, timer).await;
match result {
Err(Error::NetworkError(smoltcp::Error::Illegal)) => info!("peer closed connection"),
Err(error) => warn!("connection terminated: {}", error),
_ => (),
}
let _ = handle_connection(&stream, timer)
.await
.map_err(|e| warn!("connection terminated: {}", e));
let _ = stream.flush().await;
let _ = stream.abort().await;
});

54
src/runtime/src/net_settings.rs Normal file
View File

@ -0,0 +1,54 @@
use core::fmt;
use libboard_zynq::smoltcp::wire::{EthernetAddress, IpAddress};
use crate::config;
pub struct NetAddresses {
pub hardware_addr: EthernetAddress,
pub ipv4_addr: IpAddress,
pub ipv6_ll_addr: IpAddress,
pub ipv6_addr: Option<IpAddress>
}
impl fmt::Display for NetAddresses {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
write!(f, "MAC={} IPv4={} IPv6-LL={} IPv6=",
self.hardware_addr, self.ipv4_addr, self.ipv6_ll_addr)?;
match self.ipv6_addr {
Some(addr) => write!(f, "{}", addr)?,
None => write!(f, "no configured address")?
}
Ok(())
}
}
pub fn get_adresses(cfg: &config::Config) -> NetAddresses {
let mut hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x52]);
let mut ipv4_addr = IpAddress::v4(192, 168, 1, 52);
let mut ipv6_addr = None;
if let Ok(Ok(addr)) = cfg.read_str("mac").map(|s| s.parse()) {
hardware_addr = addr;
}
if let Ok(Ok(addr)) = cfg.read_str("ip").map(|s| s.parse()) {
ipv4_addr = addr;
}
if let Ok(Ok(addr)) = cfg.read_str("ip6").map(|s| s.parse()) {
ipv6_addr = Some(addr);
}
let ipv6_ll_addr = IpAddress::v6(
0xfe80, 0x0000, 0x0000, 0x0000,
(((hardware_addr.0[0] ^ 0x02) as u16) << 8) | (hardware_addr.0[1] as u16),
((hardware_addr.0[2] as u16) << 8) | 0x00ff,
0xfe00 | (hardware_addr.0[3] as u16),
((hardware_addr.0[4] as u16) << 8) | (hardware_addr.0[5] as u16));
NetAddresses {
hardware_addr: hardware_addr,
ipv4_addr: ipv4_addr,
ipv6_ll_addr: ipv6_ll_addr,
ipv6_addr: ipv6_addr
}
}

17
src/runtime/src/panic.rs
View File

@ -1,21 +1,8 @@
use libboard_zynq::{print, println};
use libregister::RegisterR;
use libcortex_a9::regs::MPIDR;
use unwind::backtrace;
static mut PANICKED: [bool; 2] = [false; 2];
#[panic_handler]
fn panic(info: &core::panic::PanicInfo) -> ! {
let id = MPIDR.read().cpu_id() as usize;
print!("Core {} ", id);
unsafe {
if PANICKED[id] {
println!("nested panic!");
loop {}
}
PANICKED[id] = true;
}
print!("panic at ");
if let Some(location) = info.location() {
print!("{}:{}:{}", location.file(), location.line(), location.column());
@ -31,9 +18,9 @@ fn panic(info: &core::panic::PanicInfo) -> ! {
let _ = backtrace(|ip| {
// Backtrace gives us the return address, i.e. the address after the delay slot,
// but we're interested in the call instruction.
print!("{:#08x} ", ip - 2 * 4);
println!("{:#08x}", ip - 2 * 4);
});
println!("\nEnd backtrace");
println!("End backtrace");
loop {}
}

99
src/runtime/src/proto_async.rs
View File

@ -1,66 +1,73 @@
use core::task::Poll;
use core::cmp::min;
use core::cell::RefCell;
use libboard_zynq::smoltcp;
use libasync::smoltcp::TcpStream;
type Result<T> = core::result::Result<T, smoltcp::Error>;
// TODO: use byteorder, make it more like libio
enum RecvState<T> {
NeedsMore(usize, T), // bytes consumed so far, partial result
Completed(T), // final result
}
pub type Result<T> = core::result::Result<T, smoltcp::Error>;
pub async fn expect(stream: &TcpStream, pattern: &[u8]) -> Result<bool> {
let mut state = RecvState::NeedsMore(0, true);
loop {
state = stream.recv(|buf| {
let mut consumed = 0;
if let RecvState::NeedsMore(mut cur_index, _) = state {
for b in buf.iter() {
consumed += 1;
if *b == pattern[cur_index] {
if cur_index + 1 == pattern.len() {
return (consumed, RecvState::Completed(true));
}
} else {
return (consumed, RecvState::Completed(false));
}
cur_index += 1;
stream.recv(|buf| {
for (i, b) in buf.iter().enumerate() {
if *b == pattern[i] {
if i + 1 == pattern.len() {
return Poll::Ready((i + 1, Ok(true)));
}
(consumed, RecvState::NeedsMore(cur_index, true))
} else {
unreachable!();
return Poll::Ready((i + 1, Ok(false)));
}
}).await?;
if let RecvState::Completed(result) = state {
return Ok(result);
}
}
Poll::Pending
}).await?
}
pub async fn read_bool(stream: &TcpStream) -> Result<bool> {
Ok(stream.recv(|buf| {
(1, buf[0] != 0)
Poll::Ready((1, buf[0] != 0))
}).await?)
}
pub async fn read_i8(stream: &TcpStream) -> Result<i8> {
Ok(stream.recv(|buf| {
(1, buf[0] as i8)
Poll::Ready((1, buf[0] as i8))
}).await?)
}
pub async fn read_i32(stream: &TcpStream) -> Result<i32> {
let mut buffer: [u8; 4] = [0; 4];
read_chunk(stream, &mut buffer).await?;
Ok(i32::from_be_bytes(buffer))
Ok(stream.recv(|buf| {
if buf.len() >= 4 {
let value =
((buf[0] as i32) << 24)
| ((buf[1] as i32) << 16)
| ((buf[2] as i32) << 8)
| (buf[3] as i32);
Poll::Ready((4, value))
} else {
Poll::Pending
}
}).await?)
}
pub async fn read_i64(stream: &TcpStream) -> Result<i64> {
let mut buffer: [u8; 8] = [0; 8];
read_chunk(stream, &mut buffer).await?;
Ok(i64::from_be_bytes(buffer))
Ok(stream.recv(|buf| {
if buf.len() >= 8 {
let value =
((buf[0] as i64) << 56)
| ((buf[1] as i64) << 48)
| ((buf[2] as i64) << 40)
| ((buf[3] as i64) << 32)
| ((buf[4] as i64) << 24)
| ((buf[5] as i64) << 16)
| ((buf[6] as i64) << 8)
| (buf[7] as i64);
Poll::Ready((8, value))
} else {
Poll::Pending
}
}).await?)
}
pub async fn read_chunk(stream: &TcpStream, destination: &mut [u8]) -> Result<()> {
@ -72,7 +79,7 @@ pub async fn read_chunk(stream: &TcpStream, destination: &mut [u8]) -> Result<()
let mut destination = destination.borrow_mut();
let count = min(total - done, buf.len());
destination[done..done + count].copy_from_slice(&buf[..count]);
(count, count)
Poll::Ready((count, count))
}).await?;
done += count;
}
@ -80,27 +87,39 @@ pub async fn read_chunk(stream: &TcpStream, destination: &mut [u8]) -> Result<()
}
pub async fn write_i8(stream: &TcpStream, value: i8) -> Result<()> {
stream.send_slice(&[value as u8]).await?;
stream.send([value as u8].iter().copied()).await?;
Ok(())
}
pub async fn write_bool(stream: &TcpStream, value: bool) -> Result<()> {
stream.send_slice(&[value as u8]).await?;
stream.send([value as u8].iter().copied()).await?;
Ok(())
}
pub async fn write_i32(stream: &TcpStream, value: i32) -> Result<()> {
stream.send_slice(&value.to_be_bytes()).await?;
stream.send([
(value >> 24) as u8,
(value >> 16) as u8,
(value >> 8) as u8,
value as u8].iter().copied()).await?;
Ok(())
}
pub async fn write_i64(stream: &TcpStream, value: i64) -> Result<()> {
stream.send_slice(&value.to_be_bytes()).await?;
stream.send([
(value >> 56) as u8,
(value >> 48) as u8,
(value >> 40) as u8,
(value >> 32) as u8,
(value >> 24) as u8,
(value >> 16) as u8,
(value >> 8) as u8,
value as u8].iter().copied()).await?;
Ok(())
}
pub async fn write_chunk(stream: &TcpStream, value: &[u8]) -> Result<()> {
write_i32(stream, value.len() as i32).await?;
stream.send_slice(value).await?;
stream.send(value.iter().copied()).await?;
Ok(())
}

216
src/runtime/src/rpc.rs
View File

@ -2,7 +2,6 @@ use core::str;
use core::future::Future;
use cslice::{CSlice, CMutSlice};
use log::trace;
use byteorder::{NetworkEndian, ByteOrder};
use core_io::{Write, Error};
use libboard_zynq::smoltcp;
@ -14,18 +13,6 @@ use crate::proto_core_io::ProtoWrite;
use crate::proto_async;
use self::tag::{Tag, TagIterator, split_tag};
unsafe fn align_ptr<T>(ptr: *const ()) -> *const T {
let alignment = core::mem::align_of::<T>() as isize;
let fix = (alignment - (ptr as isize) % alignment) % alignment;
((ptr as isize) + fix) as *const T
}
unsafe fn align_ptr_mut<T>(ptr: *mut ()) -> *mut T {
let alignment = core::mem::align_of::<T>() as isize;
let fix = (alignment - (ptr as isize) % alignment) % alignment;
((ptr as isize) + fix) as *mut T
}
#[async_recursion(?Send)]
async unsafe fn recv_value<F>(stream: &TcpStream, tag: Tag<'async_recursion>, data: &mut *mut (),
alloc: &(impl Fn(usize) -> F + 'async_recursion))
@ -34,7 +21,7 @@ async unsafe fn recv_value<F>(stream: &TcpStream, tag: Tag<'async_recursion>, da
{
macro_rules! consume_value {
($ty:ty, |$ptr:ident| $map:expr) => ({
let $ptr = align_ptr_mut::<$ty>(*data);
let $ptr = (*data) as *mut $ty;
*data = $ptr.offset(1) as *mut ();
$map
})
@ -73,89 +60,17 @@ async unsafe fn recv_value<F>(stream: &TcpStream, tag: Tag<'async_recursion>, da
}
Ok(())
}
Tag::List(it) => {
#[repr(C)]
Tag::List(it) | Tag::Array(it) => {
struct List { elements: *mut (), length: u32 };
consume_value!(List, |ptr| {
let length = proto_async::read_i32(stream).await? as usize;
(*ptr).length = length as u32;
(*ptr).length = proto_async::read_i32(stream).await? as u32;
let tag = it.clone().next().expect("truncated tag");
let mut data = alloc(tag.size() * length as usize).await;
(*ptr).elements = alloc(tag.size() * (*ptr).length as usize).await;
(*ptr).elements = data;
match tag {
Tag::Bool => {
let ptr = align_ptr_mut::<u8>(data);
let dest = core::slice::from_raw_parts_mut(ptr, length);
proto_async::read_chunk(stream, dest).await?;
},
Tag::Int32 => {
let ptr = align_ptr_mut::<u32>(data);
// reading as raw bytes and do endianness conversion later
let dest = core::slice::from_raw_parts_mut(ptr as *mut u8, length * 4);
proto_async::read_chunk(stream, dest).await?;
drop(dest);
let dest = core::slice::from_raw_parts_mut(ptr, length);
NetworkEndian::from_slice_u32(dest);
},
Tag::Int64 | Tag::Float64 => {
let ptr = align_ptr_mut::<u64>(data);
let dest = core::slice::from_raw_parts_mut(ptr as *mut u8, length * 8);
proto_async::read_chunk(stream, dest).await?;
drop(dest);
let dest = core::slice::from_raw_parts_mut(ptr, length);
NetworkEndian::from_slice_u64(dest);
},
_ => {
for _ in 0..(*ptr).length as usize {
recv_value(stream, tag, &mut data, alloc).await?
}
}
}
Ok(())
})
}
Tag::Array(it, num_dims) => {
consume_value!(*mut (), |buffer| {
let mut total_len: u32 = 1;
for _ in 0..num_dims {
let len = proto_async::read_i32(stream).await? as u32;
total_len *= len;
consume_value!(u32, |ptr| *ptr = len )
}
let elt_tag = it.clone().next().expect("truncated tag");
*buffer = alloc(elt_tag.size() * total_len as usize).await;
let length = total_len as usize;
let mut data = *buffer;
match elt_tag {
Tag::Bool => {
let ptr = align_ptr_mut::<u8>(data);
let dest = core::slice::from_raw_parts_mut(ptr, length);
proto_async::read_chunk(stream, dest).await?;
},
Tag::Int32 => {
let ptr = align_ptr_mut::<u32>(data);
let dest = core::slice::from_raw_parts_mut(ptr as *mut u8, length * 4);
proto_async::read_chunk(stream, dest).await?;
drop(dest);
let dest = core::slice::from_raw_parts_mut(ptr, length);
NetworkEndian::from_slice_u32(dest);
},
Tag::Int64 | Tag::Float64 => {
let ptr = align_ptr_mut::<u64>(data);
let dest = core::slice::from_raw_parts_mut(ptr as *mut u8, length * 8);
proto_async::read_chunk(stream, dest).await?;
drop(dest);
let dest = core::slice::from_raw_parts_mut(ptr, length);
NetworkEndian::from_slice_u64(dest);
},
_ => {
for _ in 0..length {
recv_value(stream, elt_tag, &mut data, alloc).await?
}
}
let mut data = (*ptr).elements;
for _ in 0..(*ptr).length as usize {
recv_value(stream, tag, &mut data, alloc).await?
}
Ok(())
})
@ -193,7 +108,7 @@ unsafe fn send_value<W>(writer: &mut W, tag: Tag, data: &mut *const ())
{
macro_rules! consume_value {
($ty:ty, |$ptr:ident| $map:expr) => ({
let $ptr = align_ptr::<$ty>(*data);
let $ptr = (*data) as *const $ty;
*data = $ptr.offset(1) as *const ();
$map
})
@ -226,104 +141,15 @@ unsafe fn send_value<W>(writer: &mut W, tag: Tag, data: &mut *const ())
}
Ok(())
}
Tag::List(it) => {
#[repr(C)]
Tag::List(it) | Tag::Array(it) => {
struct List { elements: *const (), length: u32 };
consume_value!(List, |ptr| {
let length = (*ptr).length as isize;
writer.write_u32((*ptr).length)?;
let tag = it.clone().next().expect("truncated tag");
let mut data = (*ptr).elements;
writer.write_u8(tag.as_u8())?;
match tag {
Tag::Bool => {
// we can pretend this is u8...
let ptr1 = align_ptr::<u8>(data);
let slice = core::slice::from_raw_parts(ptr1, length as usize);
writer.write_all(slice)?;
},
Tag::Int32 => {
let ptr1 = align_ptr::<i32>(data);
let slice = core::slice::from_raw_parts(ptr1, length as usize);
let mut v: alloc::vec::Vec<i32> = slice.to_vec();
NetworkEndian::from_slice_i32(&mut v);
let slice2 = core::slice::from_raw_parts(
v.as_ptr() as usize as *const u8,
length as usize * 4
);
writer.write_all(slice2)?;
},
Tag::Int64 | Tag::Float64 => {
let ptr1 = align_ptr::<i64>(data);
let slice = core::slice::from_raw_parts(ptr1, length as usize);
let mut v: alloc::vec::Vec<i64> = slice.to_vec();
NetworkEndian::from_slice_i64(&mut v);
let slice2 = core::slice::from_raw_parts(
v.as_ptr() as usize as *const u8,
length as usize * 8
);
writer.write_all(slice2)?;
},
// non-primitive types, not sure if this would happen but we can handle it...
_ => {
for _ in 0..length {
send_value(writer, tag, &mut data)?;
}
}
};
Ok(())
})
}
Tag::Array(it, num_dims) => {
writer.write_u8(num_dims)?;
consume_value!(*const(), |buffer| {
let elt_tag = it.clone().next().expect("truncated tag");
let mut total_len = 1;
for _ in 0..num_dims {
consume_value!(u32, |len| {
writer.write_u32(*len)?;
total_len *= *len;
})
for _ in 0..(*ptr).length as usize {
send_value(writer, tag, &mut data)?;
}
let mut data = *buffer;
let length = total_len as isize;
writer.write_u8(elt_tag.as_u8())?;
match elt_tag {
Tag::Bool => {
let ptr1 = align_ptr::<u8>(data);
let slice = core::slice::from_raw_parts(ptr1, length as usize);
writer.write_all(slice)?;
},
Tag::Int32 => {
let ptr1 = align_ptr::<i32>(data);
let slice = core::slice::from_raw_parts(ptr1, length as usize);
let mut v: alloc::vec::Vec<i32> = slice.to_vec();
NetworkEndian::from_slice_i32(&mut v);
let slice2 = core::slice::from_raw_parts(
v.as_ptr() as usize as *const u8,
length as usize * 4
);
writer.write_all(slice2)?;
},
Tag::Int64 | Tag::Float64 => {
let ptr1 = align_ptr::<i64>(data);
let slice = core::slice::from_raw_parts(ptr1, length as usize);
let mut v: alloc::vec::Vec<i64> = slice.to_vec();
NetworkEndian::from_slice_i64(&mut v);
let slice2 = core::slice::from_raw_parts(
v.as_ptr() as usize as *const u8,
length as usize * 8
);
writer.write_all(slice2)?;
},
// non-primitive types, not sure if this would happen but we can handle it...
_ => {
for _ in 0..length {
send_value(writer, elt_tag, &mut data)?;
}
}
};
Ok(())
})
}
@ -335,7 +161,6 @@ unsafe fn send_value<W>(writer: &mut W, tag: Tag, data: &mut *const ())
Ok(())
}
Tag::Keyword(it) => {
#[repr(C)]
struct Keyword<'a> { name: CSlice<'a, u8> };
consume_value!(Keyword, |ptr| {
writer.write_string(str::from_utf8((*ptr).name.as_ref()).unwrap())?;
@ -347,7 +172,6 @@ unsafe fn send_value<W>(writer: &mut W, tag: Tag, data: &mut *const ())
// to accurately advance data.
}
Tag::Object => {
#[repr(C)]
struct Object { id: u32 };
consume_value!(*const Object, |ptr|
writer.write_u32((**ptr).id))
@ -405,7 +229,7 @@ mod tag {
ByteArray,
Tuple(TagIterator<'a>, u8),
List(TagIterator<'a>),
Array(TagIterator<'a>, u8),
Array(TagIterator<'a>),
Range(TagIterator<'a>),
Keyword(TagIterator<'a>),
Object
@ -424,7 +248,7 @@ mod tag {
Tag::ByteArray => b'A',
Tag::Tuple(_, _) => b't',
Tag::List(_) => b'l',
Tag::Array(_, _) => b'a',
Tag::Array(_) => b'a',
Tag::Range(_) => b'r',
Tag::Keyword(_) => b'k',
Tag::Object => b'O',
@ -451,7 +275,7 @@ mod tag {
size
}
Tag::List(_) => 8,
Tag::Array(_, num_dims) => 4 * (1 + num_dims as usize),
Tag::Array(_) => 8,
Tag::Range(it) => {
let tag = it.clone().next().expect("truncated tag");
tag.size() * 3
@ -494,11 +318,7 @@ mod tag {
Tag::Tuple(self.sub(count), count)
}
b'l' => Tag::List(self.sub(1)),
b'a' => {
let count = self.data[0];
self.data = &self.data[1..];
Tag::Array(self.sub(1), count)
}
b'a' => Tag::Array(self.sub(1)),
b'r' => Tag::Range(self.sub(1)),
b'k' => Tag::Keyword(self.sub(1)),
b'O' => Tag::Object,
@ -553,10 +373,10 @@ mod tag {
it.fmt(f)?;
write!(f, ")")?;
}
Tag::Array(it, num_dims) => {
Tag::Array(it) => {
write!(f, "Array(")?;
it.fmt(f)?;
write!(f, ", {})", num_dims)?;
write!(f, ")")?;
}
Tag::Range(it) => {
write!(f, "Range(")?;

55
src/runtime/src/rtio_csr.rs → src/runtime/src/rtio.rs
View File

@ -1,6 +1,6 @@
use core::ptr::{read_volatile, write_volatile};
use cslice::CSlice;
use log::error;
use crate::artiq_raise;
use crate::pl::csr;
@ -124,17 +124,16 @@ pub extern fn input_timestamp(timeout: i64, channel: i32) -> i64 {
}
if status & RTIO_I_STATUS_OVERFLOW != 0 {
artiq_raise!("RTIOOverflow",
"RTIO input overflow on channel {0}",
channel as i64, 0, 0);
csr::rtio::i_overflow_reset_write(1);
error!("RTIO input overflow on channel {0}",
channel as i64);
}
if status & RTIO_I_STATUS_WAIT_EVENT != 0 {
return -1
}
if status & RTIO_I_STATUS_DESTINATION_UNREACHABLE != 0 {
artiq_raise!("RTIODestinationUnreachable",
"RTIO destination unreachable, input, on channel {0}",
channel as i64, 0, 0);
error!("RTIO destination unreachable, input, on channel {0}",
channel as i64);
}
csr::rtio::i_timestamp_read() as i64
@ -152,14 +151,13 @@ pub extern fn input_data(channel: i32) -> i32 {
}
if status & RTIO_I_STATUS_OVERFLOW != 0 {
artiq_raise!("RTIOOverflow",
"RTIO input overflow on channel {0}",
channel as i64, 0, 0);
csr::rtio::i_overflow_reset_write(1);
error!("RTIO input overflow on channel {0}",
channel as i64);
}
if status & RTIO_I_STATUS_DESTINATION_UNREACHABLE != 0 {
artiq_raise!("RTIODestinationUnreachable",
"RTIO destination unreachable, input, on channel {0}",
channel as i64, 0, 0);
error!("RTIO destination unreachable, input, on channel {0}",
channel as i64);
}
rtio_i_data_read(0) as i32
@ -177,17 +175,16 @@ pub extern fn input_timestamped_data(timeout: i64, channel: i32) -> TimestampedD
}
if status & RTIO_I_STATUS_OVERFLOW != 0 {
artiq_raise!("RTIOOverflow",
"RTIO input overflow on channel {0}",
channel as i64, 0, 0);
csr::rtio::i_overflow_reset_write(1);
error!("RTIO input overflow on channel {0}",
channel as i64);
}
if status & RTIO_I_STATUS_WAIT_EVENT != 0 {
return TimestampedData { timestamp: -1, data: 0 }
}
if status & RTIO_I_STATUS_DESTINATION_UNREACHABLE != 0 {
artiq_raise!("RTIODestinationUnreachable",
"RTIO destination unreachable, input, on channel {0}",
channel as i64, 0, 0);
error!("RTIO destination unreachable, input, on channel {0}",
channel as i64);
}
TimestampedData {
@ -196,23 +193,3 @@ pub extern fn input_timestamped_data(timeout: i64, channel: i32) -> TimestampedD
}
}
}
pub fn write_log(data: &[i8]) {
unsafe {
csr::rtio::target_write(csr::CONFIG_RTIO_LOG_CHANNEL << 8);
let mut word: u32 = 0;
for i in 0..data.len() {
word <<= 8;
word |= data[i] as u32;
if i % 4 == 3 {
rtio_o_data_write(0, word);
word = 0;
}
}
if word != 0 {
rtio_o_data_write(0, word);
}
}
}

287
src/runtime/src/rtio_acp.rs
View File

@ -1,287 +0,0 @@
use cslice::CSlice;
use vcell::VolatileCell;
use libcortex_a9::asm;
use crate::artiq_raise;
use core::sync::atomic::{fence, Ordering};
use crate::pl::csr;
pub const RTIO_O_STATUS_WAIT: i32 = 1;
pub const RTIO_O_STATUS_UNDERFLOW: i32 = 2;
pub const RTIO_O_STATUS_DESTINATION_UNREACHABLE: i32 = 4;
pub const RTIO_I_STATUS_WAIT_EVENT: i32 = 1;
pub const RTIO_I_STATUS_OVERFLOW: i32 = 2;
pub const RTIO_I_STATUS_WAIT_STATUS: i32 = 4; // TODO
pub const RTIO_I_STATUS_DESTINATION_UNREACHABLE: i32 = 8;
#[repr(C)]
pub struct TimestampedData {
timestamp: i64,
data: i32,
}
#[repr(C, align(64))]
struct Transaction {
request_cmd: i8,
data_width: i8,
padding0: [i8; 2],
request_target: i32,
request_timestamp: i64,
request_data: [i32; 16],
padding1: [i64; 2],
reply_status: VolatileCell<i32>,
reply_data: VolatileCell<i32>,
reply_timestamp: VolatileCell<i64>,
padding2: [i64; 2],
}
static mut TRANSACTION_BUFFER: Transaction = Transaction {
request_cmd: 0,
data_width: 0,
request_target: 0,
request_timestamp: 0,
request_data: [0; 16],
reply_status: VolatileCell::new(0),
reply_data: VolatileCell::new(0),
reply_timestamp: VolatileCell::new(0),
padding0: [0; 2],
padding1: [0; 2],
padding2: [0; 2]
};
pub extern fn init() {
unsafe {
csr::rtio_core::reset_write(1);
csr::rtio::engine_addr_base_write(&TRANSACTION_BUFFER as *const Transaction as u32);
csr::rtio::enable_write(1);
}
}
pub extern fn get_destination_status(destination: i32) -> bool {
// TODO
destination == 0
}
pub extern fn get_counter() -> i64 {
unsafe {
csr::rtio::counter_update_write(1);
csr::rtio::counter_read() as i64
}
}
static mut NOW: i64 = 0;
pub extern fn now_mu() -> i64 {
unsafe { NOW }
}
pub extern fn at_mu(t: i64) {
unsafe { NOW = t }
}
pub extern fn delay_mu(dt: i64) {
unsafe { NOW += dt }
}
#[inline(never)]
unsafe fn process_exceptional_status(channel: i32, status: i32) {
let timestamp = now_mu();
if status & RTIO_O_STATUS_WAIT != 0 {
// FIXME: this is a kludge and probably buggy (kernel interrupted?)
while csr::rtio::o_status_read() as i32 & RTIO_O_STATUS_WAIT != 0 {}
}
if status & RTIO_O_STATUS_UNDERFLOW != 0 {
artiq_raise!("RTIOUnderflow",
"RTIO underflow at {0} mu, channel {1}, slack {2} mu",
timestamp, channel as i64, timestamp - get_counter());
}
if status & RTIO_O_STATUS_DESTINATION_UNREACHABLE != 0 {
artiq_raise!("RTIODestinationUnreachable",
"RTIO destination unreachable, output, at {0} mu, channel {1}",
timestamp, channel as i64, 0);
}
}
pub extern fn output(target: i32, data: i32) {
unsafe {
// Clear status so we can observe response
TRANSACTION_BUFFER.reply_status.set(0);
TRANSACTION_BUFFER.request_cmd = 0;
TRANSACTION_BUFFER.data_width = 1;
TRANSACTION_BUFFER.request_target = target;
TRANSACTION_BUFFER.request_timestamp = NOW;
TRANSACTION_BUFFER.request_data[0] = data;
fence(Ordering::SeqCst);
asm::sev();
let mut status;
loop {
status = TRANSACTION_BUFFER.reply_status.get();
if status != 0 {
break;
}
}
let status = status & !0x10000;
if status != 0 {
process_exceptional_status(target >> 8, status);
}
}
}
pub extern fn output_wide(target: i32, data: CSlice<i32>) {
unsafe {
// Clear status so we can observe response
TRANSACTION_BUFFER.reply_status.set(0);
TRANSACTION_BUFFER.request_cmd = 0;
TRANSACTION_BUFFER.data_width = data.len() as i8;
TRANSACTION_BUFFER.request_target = target;
TRANSACTION_BUFFER.request_timestamp = NOW;
TRANSACTION_BUFFER.request_data[..data.len()].copy_from_slice(data.as_ref());
fence(Ordering::SeqCst);
asm::sev();
let mut status;
loop {
status = TRANSACTION_BUFFER.reply_status.get();
if status != 0 {
break
}
}
let status = status & !0x10000;
if status != 0 {
process_exceptional_status(target >> 8, status);
}
}
}
pub extern fn input_timestamp(timeout: i64, channel: i32) -> i64 {
unsafe {
// Clear status so we can observe response
TRANSACTION_BUFFER.reply_status.set(0);
TRANSACTION_BUFFER.request_cmd = 1;
TRANSACTION_BUFFER.request_timestamp = timeout;
TRANSACTION_BUFFER.request_target = channel << 8;
TRANSACTION_BUFFER.data_width = 0;
fence(Ordering::SeqCst);
asm::sev();
let mut status;
loop {
status = TRANSACTION_BUFFER.reply_status.get();
if status != 0 {
break
}
}
if status & RTIO_I_STATUS_OVERFLOW != 0 {
artiq_raise!("RTIOOverflow",
"RTIO input overflow on channel {0}",
channel as i64, 0, 0);
}
if status & RTIO_I_STATUS_WAIT_EVENT != 0 {
return -1
}
if status & RTIO_I_STATUS_DESTINATION_UNREACHABLE != 0 {
artiq_raise!("RTIODestinationUnreachable",
"RTIO destination unreachable, input, on channel {0}",
channel as i64, 0, 0);
}
TRANSACTION_BUFFER.reply_timestamp.get()
}
}
pub extern fn input_data(channel: i32) -> i32 {
unsafe {
TRANSACTION_BUFFER.reply_status.set(0);
TRANSACTION_BUFFER.request_cmd = 1;
TRANSACTION_BUFFER.request_timestamp = -1;
TRANSACTION_BUFFER.request_target = channel << 8;
TRANSACTION_BUFFER.data_width = 0;
fence(Ordering::SeqCst);
asm::sev();
let mut status;
loop {
status = TRANSACTION_BUFFER.reply_status.get();
if status != 0 {
break
}
}
if status & RTIO_I_STATUS_OVERFLOW != 0 {
artiq_raise!("RTIOOverflow",
"RTIO input overflow on channel {0}",
channel as i64, 0, 0);
}
if status & RTIO_I_STATUS_DESTINATION_UNREACHABLE != 0 {
artiq_raise!("RTIODestinationUnreachable",
"RTIO destination unreachable, input, on channel {0}",
channel as i64, 0, 0);
}
TRANSACTION_BUFFER.reply_data.get()
}
}
pub extern fn input_timestamped_data(timeout: i64, channel: i32) -> TimestampedData {
unsafe {
TRANSACTION_BUFFER.reply_status.set(0);
TRANSACTION_BUFFER.request_cmd = 1;
TRANSACTION_BUFFER.request_timestamp = timeout;
TRANSACTION_BUFFER.request_target = channel << 8;
TRANSACTION_BUFFER.data_width = 0;
fence(Ordering::SeqCst);
asm::sev();
let mut status;
loop {
status = TRANSACTION_BUFFER.reply_status.get();
if status != 0 {
break
}
}
if status & RTIO_I_STATUS_OVERFLOW != 0 {
artiq_raise!("RTIOOverflow",
"RTIO input overflow on channel {0}",
channel as i64, 0, 0);
}
if status & RTIO_I_STATUS_DESTINATION_UNREACHABLE != 0 {
artiq_raise!("RTIODestinationUnreachable",
"RTIO destination unreachable, input, on channel {0}",
channel as i64, 0, 0);
}
TimestampedData {
timestamp: TRANSACTION_BUFFER.reply_timestamp.get(),
data: TRANSACTION_BUFFER.reply_data.get(),
}
}
}
pub fn write_log(data: &[i8]) {
let mut word: u32 = 0;
for i in 0..data.len() {
word <<= 8;
word |= data[i] as u32;
if i % 4 == 3 {
output((csr::CONFIG_RTIO_LOG_CHANNEL << 8) as i32, word as i32);
word = 0;
}
}
if word != 0 {
output((csr::CONFIG_RTIO_LOG_CHANNEL << 8) as i32, word as i32);
}
}

303
src/runtime/src/sd_reader.rs Normal file
View File

@ -0,0 +1,303 @@
use core_io::{BufRead, Error, ErrorKind, Read, Result as IoResult, Seek, SeekFrom, Write};
use fatfs;
use libboard_zynq::sdio::{sd_card::SdCard, CmdTransferError};
use log::debug;
use alloc::vec::Vec;
const MBR_SIGNATURE: [u8; 2] = [0x55, 0xAA];
const PARTID_FAT12: u8 = 0x01;
const PARTID_FAT16_LESS32M: u8 = 0x04;
const PARTID_FAT16: u8 = 0x06;
const PARTID_FAT32: u8 = 0x0B;
const PARTID_FAT32_LBA: u8 = 0x0C;
fn cmd_error_to_io_error(_: CmdTransferError) -> Error {
Error::new(ErrorKind::Other, "Command transfer error")
}
const BLOCK_SIZE: usize = 512;
/// SdReader struct implementing `Read + BufRead + Write + Seek` traits for `core_io`.
/// Used as an adaptor for fatfs crate, but could be used directly for raw data access.
///
/// Implementation: all read/writes would be split into unaligned and block-aligned parts,
/// unaligned read/writes would do a buffered read/write using a block-sized internal buffer,
/// while aligned transactions would be sent to the SD card directly for performance reason.
pub struct SdReader {
/// Internal SdCard handle.
sd: SdCard,
/// Read buffer with the size of 1 block.
buffer: Vec<u8>,
/// Address for the next byte.
byte_addr: u32,
/// Internal index for the next byte.
/// Normally in range `[0, BLOCK_SIZE - 1]`.
///
/// `index = BLOCK_SIZE` means that the `buffer` is invalid for the current `byte_addr`,
/// the next `fill_buf` call would fill the buffer.
index: usize,
/// Dirty flag indicating the content has to be flushed.
dirty: bool,
/// Base offset for translation from logical address to physical address.
offset: u32,
}
#[derive(Copy, Clone)]
#[allow(unused)]
// Partition entry enum, normally we would use entry1.
pub enum PartitionEntry {
Entry1 = 0x1BE,
Entry2 = 0x1CE,
Entry3 = 0x1DE,
Entry4 = 0x1EE,
}
impl SdReader {
/// Create SdReader from SdCard
pub fn new(sd: SdCard) -> SdReader {
let mut vec: Vec<u8> = Vec::with_capacity(BLOCK_SIZE);
unsafe {
vec.set_len(vec.capacity());
}
SdReader {
sd,
buffer: vec,
byte_addr: 0,
index: BLOCK_SIZE,
dirty: false,
offset: 0,
}
}
/// Internal read function for unaligned read.
/// The read must not cross block boundary.
fn read_unaligned(&mut self, buf: &mut [u8]) -> IoResult<usize> {
if buf.len() == 0 {
return Ok(0);
}
let filled_buffer = self.fill_buf()?;
for (dest, src) in buf.iter_mut().zip(filled_buffer.iter()) {
*dest = *src;
}
self.consume(buf.len());
Ok(buf.len())
}
/// Internal write function for unaligned write.
/// The write must not cross block boundary.
fn write_unaligned(&mut self, buf: &[u8]) -> IoResult<usize> {
if buf.len() == 0 {
return Ok(0);
}
// update buffer if needed, as we will flush the entire block later.
self.fill_buf()?;
self.dirty = true;
let dest_buffer = &mut self.buffer[self.index..];
for (src, dest) in buf.iter().zip(dest_buffer.iter_mut()) {
*dest = *src;
}
self.consume(buf.len());
Ok(buf.len())
}
/// Split the slice into three segments, with the middle block-aligned.
/// Alignment depends on the current `self.byte_addr` instead of the slice pointer address
fn block_align<'b>(&self, buf: &'b [u8]) -> (&'b [u8], &'b [u8], &'b [u8]) {
let head_len = BLOCK_SIZE - (self.byte_addr as usize % BLOCK_SIZE);
if head_len > buf.len() {
(buf, &[], &[])
} else {
let remaining_length = buf.len() - head_len;
let mid_length = remaining_length - remaining_length % BLOCK_SIZE;
let (head, remaining) = buf.split_at(head_len);
let (mid, tail) = remaining.split_at(mid_length);
(head, mid, tail)
}
}
/// Split the mutable slice into three segments, with the middle block-aligned.
/// Alignment depends on the current `self.byte_addr` instead of the slice pointer address
fn block_align_mut<'b>(&self, buf: &'b mut [u8]) -> (&'b mut [u8], &'b mut [u8], &'b mut [u8]) {
let head_len = BLOCK_SIZE - (self.byte_addr as usize % BLOCK_SIZE);
if head_len > buf.len() {
(buf, &mut [], &mut [])
} else {
let remaining_length = buf.len() - head_len;
let mid_length = remaining_length - remaining_length % BLOCK_SIZE;
let (head, remaining) = buf.split_at_mut(head_len);
let (mid, tail) = remaining.split_at_mut(mid_length);
(head, mid, tail)
}
}
/// Invalidate the buffer, so later unaligned read/write would reload the buffer from SD card.
fn invalidate_buffer(&mut self) {
self.index = BLOCK_SIZE;
}
/// Set the base offset of the SD card, to transform from physical address to logical address.
fn set_base_offset(&mut self, offset: u32) -> IoResult<u64> {
self.offset = offset;
self.seek(SeekFrom::Start(0))
}
/// Mount fatfs from partition entry, and return the fatfs object if success.
/// This takes the ownership of self, so currently there is no way to recover from an error,
/// except creating a new SD card instance.
pub fn mount_fatfs(mut self, entry: PartitionEntry) -> IoResult<fatfs::FileSystem<Self>> {
let mut buffer: [u8; 4] = [0; 4];
self.seek(SeekFrom::Start(0x1FE))?;
self.read_exact(&mut buffer[..2])?;
// check MBR signature
if buffer[..2] != MBR_SIGNATURE {
return Err(Error::new(
ErrorKind::InvalidData,
"Incorrect signature for MBR sector.",
));
}
// Read partition ID.
self.seek(SeekFrom::Start(entry as u64 + 0x4))?;
self.read_exact(&mut buffer[..1])?;
debug!("Partition ID: {:0X}", buffer[0]);
match buffer[0] {
PARTID_FAT12 | PARTID_FAT16_LESS32M | PARTID_FAT16 |
PARTID_FAT32 | PARTID_FAT32_LBA => {}
_ => {
return Err(Error::new(
ErrorKind::InvalidData,
"No FAT partition found for the specified entry.",
));
}
}
// Read LBA
self.seek(SeekFrom::Current(0x3))?;
self.read_exact(&mut buffer)?;
let mut lba: u32 = 0;
// Little endian
for i in 0..4 {
lba |= (buffer[i] as u32) << (i * 8);
}
// Set to logical address
self.set_base_offset(lba * BLOCK_SIZE as u32)?;
// setup fatfs
fatfs::FileSystem::new(self, fatfs::FsOptions::new())
}
}
impl Read for SdReader {
fn read(&mut self, buf: &mut [u8]) -> IoResult<usize> {
let total_length = buf.len();
let (a, b, c) = self.block_align_mut(buf);
self.read_unaligned(a)?;
if b.len() > 0 {
// invalidate internal buffer
self.invalidate_buffer();
if let Err(_) = self.sd.read_block(
self.byte_addr / BLOCK_SIZE as u32,
(b.len() / BLOCK_SIZE) as u16,
b,
) {
// we have to allow partial read, as per the trait required
return Ok(a.len());
}
self.byte_addr += b.len() as u32;
}
if let Err(_) = self.read_unaligned(c) {
// we have to allow partial read, as per the trait required
return Ok(a.len() + b.len());
}
Ok(total_length)
}
}
impl BufRead for SdReader {
fn fill_buf(&mut self) -> IoResult<&[u8]> {
if self.index == BLOCK_SIZE {
// flush the buffer if it is dirty before overwriting it with new data
if self.dirty {
self.flush()?;
}
// reload buffer
self.sd
.read_block(self.byte_addr / (BLOCK_SIZE as u32), 1, &mut self.buffer)
.map_err(cmd_error_to_io_error)?;
self.index = (self.byte_addr as usize) % BLOCK_SIZE;
}
Ok(&self.buffer[self.index..])
}
fn consume(&mut self, amt: usize) {
self.index += amt;
self.byte_addr += amt as u32;
}
}
impl Write for SdReader {
fn write(&mut self, buf: &[u8]) -> IoResult<usize> {
let (a, b, c) = self.block_align(buf);
self.write_unaligned(a)?;
if b.len() > 0 {
self.flush()?;
self.invalidate_buffer();
if let Err(_) = self.sd.write_block(
self.byte_addr / BLOCK_SIZE as u32,
(b.len() / BLOCK_SIZE) as u16,
b,
) {
return Ok(a.len());
}
self.byte_addr += b.len() as u32;
}
if let Err(_) = self.write_unaligned(c) {
return Ok(a.len() + b.len());
}
Ok(buf.len())
}
fn flush(&mut self) -> IoResult<()> {
if self.dirty {
let block_addr = (self.byte_addr - self.index as u32) / (BLOCK_SIZE as u32);
self.sd
.write_block(block_addr, 1, &self.buffer)
.map_err(cmd_error_to_io_error)?;
self.dirty = false;
}
Ok(())
}
}
impl Seek for SdReader {
fn seek(&mut self, pos: SeekFrom) -> IoResult<u64> {
let raw_target = match pos {
SeekFrom::Start(x) => self.offset as i64 + x as i64,
SeekFrom::Current(x) => self.byte_addr as i64 + x,
SeekFrom::End(_) => panic!("SD card does not support seek from end"),
};
if raw_target < self.offset as i64 || raw_target > core::u32::MAX as i64 {
return Err(Error::new(ErrorKind::InvalidInput, "Invalid address"));
}
let target_byte_addr = raw_target as u32;
let address_same_block =
self.byte_addr / (BLOCK_SIZE as u32) == target_byte_addr / (BLOCK_SIZE as u32);
// if the buffer was invalidated, we consider seek as different block
let same_block = address_same_block && self.index != BLOCK_SIZE;
if !same_block {
self.flush()?;
}
self.byte_addr = target_byte_addr;
self.index = if same_block {
target_byte_addr as usize % BLOCK_SIZE
} else {
// invalidate the buffer as we moved to a different block
BLOCK_SIZE
};
Ok((self.byte_addr - self.offset) as u64)
}
}
impl Drop for SdReader {
fn drop(&mut self) {
// just try to flush it, ignore error if any
self.flush().unwrap_or(());
}
}

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[package]
name = "szl"
description = "Simple Zynq Loader"
version = "0.1.0"
authors = ["M-Labs"]
edition = "2018"
[features]
target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706"]
default = ["target_zc706"]
[dependencies]
log = "0.4"
cstr_core = { version = "0.2", default-features = false }
libboard_zynq = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
libsupport_zynq = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
libcortex_a9 = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
[build-dependencies]
cc = { version = "1.0.1" }

48
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use std::env;
use std::fs::File;
use std::io::Write;
use std::path::{Path, PathBuf};
fn main() {
println!("cargo:rerun-if-changed=build.rs");
let out = env::var("OUT_DIR").unwrap();
let out_dir = &PathBuf::from(&out);
compile_unlzma();
// Put the linker script somewhere the linker can find it
File::create(out_dir.join("link.x"))
.unwrap()
.write_all(include_bytes!("link.x"))
.unwrap();
println!("cargo:rustc-link-search={}", out_dir.display());
// Only re-run the build script when link.x is changed,
// instead of when any part of the source code changes.
println!("cargo:rerun-if-changed=link.x");
}
pub fn compile_unlzma() {
let cfg = &mut cc::Build::new();
cfg.compiler("clang");
cfg.no_default_flags(true);
cfg.warnings(false);
cfg.flag("-nostdlib");
cfg.flag("-ffreestanding");
cfg.flag("-fPIC");
cfg.flag("-fno-stack-protector");
cfg.flag("--target=armv7-none-eabihf");
cfg.flag("-O2");
let sources = vec![
"unlzma.c",
];
let root = Path::new("./");
for src in sources {
println!("cargo:rerun-if-changed={}", src);
cfg.file(root.join("src").join(src));
}
cfg.compile("unlzma");
}

58
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ENTRY(Reset);
MEMORY
{
/* 256 kB On-Chip Memory */
OCM : ORIGIN = 0, LENGTH = 0x30000
OCM3 : ORIGIN = 0xFFFF0000, LENGTH = 0x10000
}
SECTIONS
{
.text :
{
KEEP(*(.text.exceptions));
*(.text.boot);
*(.text .text.*);
} > OCM
.rodata : ALIGN(4)
{
*(.rodata .rodata.*);
} > OCM
.data : ALIGN(4)
{
*(.data .data.*);
} > OCM
.bss (NOLOAD) : ALIGN(4)
{
__bss_start = .;
*(.bss .bss.*);
. = ALIGN(4);
__bss_end = .;
} > OCM3
.stack1 (NOLOAD) : ALIGN(8)
{
__stack1_end = .;
. += 0x4000;
__stack1_start = .;
} > OCM3
.stack0 (NOLOAD) : ALIGN(8)
{
__stack0_end = .;
. += 0x4000;
__stack0_start = .;
} > OCM3
/DISCARD/ :
{
/* Unused exception related info that only wastes space */
*(.ARM.exidx);
*(.ARM.exidx.*);
*(.ARM.extab.*);
}
}

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#![no_std]
#![no_main]
extern crate log;
use core::mem;
use log::{debug, info, error};
use cstr_core::CStr;
use libcortex_a9::{enable_fpu, cache::dcci_slice};
use libboard_zynq::{
self as zynq, clocks::Clocks, clocks::source::{ClockSource, ArmPll, IoPll},
logger,
timer::GlobalTimer,
};
use libsupport_zynq as _;
extern "C" {
fn unlzma_simple(buf: *const u8, in_len: i32,
output: *mut u8,
error: extern fn(*const u8)) -> i32;
}
extern fn lzma_error(message: *const u8) {
error!("LZMA error: {}", unsafe { CStr::from_ptr(message) }.to_str().unwrap());
}
#[no_mangle]
pub fn main_core0() {
GlobalTimer::start();
logger::init().unwrap();
log::set_max_level(log::LevelFilter::Debug);
info!("Simple Zynq Loader starting...");
enable_fpu();
debug!("FPU enabled on Core0");
const CPU_FREQ: u32 = 800_000_000;
ArmPll::setup(2 * CPU_FREQ);
Clocks::set_cpu_freq(CPU_FREQ);
IoPll::setup(1_000_000_000);
libboard_zynq::stdio::drop_uart(); // reinitialize UART after clocking change
let mut ddr = zynq::ddr::DdrRam::new();
let payload = include_bytes!("../../../build/szl-payload.bin.lzma");
info!("decompressing payload");
let result = unsafe {
unlzma_simple(payload.as_ptr(), payload.len() as i32, ddr.ptr(), lzma_error)
};
if result < 0 {
error!("decompression failed");
} else {
// Flush data cache entries for all of DDR, including
// Memory/Instruction Symchronization Barriers
dcci_slice(unsafe {
core::slice::from_raw_parts(ddr.ptr::<u8>(), ddr.size())
});
// Start core0 only, for compatibility with FSBL.
info!("executing payload");
unsafe {
(mem::transmute::<*mut u8, fn()>(ddr.ptr::<u8>()))();
}
}
loop {}
}
#[no_mangle]
pub fn main_core1() {
panic!("core1 started but should not have");
}

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/*
*Taken from: Lzma decompressor for Linux kernel. Shamelessly snarfed
*from busybox 1.1.1
*
*Linux kernel adaptation
*Copyright (C) 2006 Alain < alain@knaff.lu >
*
*Based on small lzma deflate implementation/Small range coder
*implementation for lzma.
*Copyright (C) 2006 Aurelien Jacobs < aurel@gnuage.org >
*
*Based on LzmaDecode.c from the LZMA SDK 4.22 (http://www.7-zip.org/)
*Copyright (C) 1999-2005 Igor Pavlov
*
*Copyrights of the parts, see headers below.
*
*
*This program is free software; you can redistribute it and/or
*modify it under the terms of the GNU Lesser General Public
*License as published by the Free Software Foundation; either
*version 2.1 of the License, or (at your option) any later version.
*
*This program is distributed in the hope that it will be useful,
*but WITHOUT ANY WARRANTY; without even the implied warranty of
*MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
*Lesser General Public License for more details.
*
*You should have received a copy of the GNU Lesser General Public
*License along with this library; if not, write to the Free Software
*Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define NULL ((void *)0)
#define alloca(size) __builtin_alloca(size)
#define malloc alloca
static inline void free(void *p) {}
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
static long long read_int(unsigned char *ptr, int size)
{
int i;
long long ret = 0;
for (i = 0; i < size; i++)
ret = (ret << 8) | ptr[size-i-1];
return ret;
}
#define ENDIAN_CONVERT(x) \
x = (typeof(x))read_int((unsigned char *)&x, sizeof(x))
/* Small range coder implementation for lzma.
*Copyright (C) 2006 Aurelien Jacobs < aurel@gnuage.org >
*
*Based on LzmaDecode.c from the LZMA SDK 4.22 (http://www.7-zip.org/)
*Copyright (c) 1999-2005 Igor Pavlov
*/
#define LZMA_IOBUF_SIZE 0x10000
struct rc {
int (*fill)(void*, unsigned int);
unsigned char *ptr;
unsigned char *buffer;
unsigned char *buffer_end;
int buffer_size;
unsigned int code;
unsigned int range;
unsigned int bound;
void (*error)(char *);
};
#define RC_TOP_BITS 24
#define RC_MOVE_BITS 5
#define RC_MODEL_TOTAL_BITS 11
static int nofill(void *buffer, unsigned int len)
{
return -1;
}
/* Called twice: once at startup and once in rc_normalize() */
static void rc_read(struct rc *rc)
{
rc->buffer_size = rc->fill((char *)rc->buffer, LZMA_IOBUF_SIZE);
if (rc->buffer_size <= 0)
rc->error("unexpected EOF");
rc->ptr = rc->buffer;
rc->buffer_end = rc->buffer + rc->buffer_size;
}
/* Called once */
static inline void rc_init(struct rc *rc,
int (*fill)(void*, unsigned int),
unsigned char *buffer, int buffer_size)
{
if (fill)
rc->fill = fill;
else
rc->fill = nofill;
rc->buffer = buffer;
rc->buffer_size = buffer_size;
rc->buffer_end = rc->buffer + rc->buffer_size;
rc->ptr = rc->buffer;
rc->code = 0;
rc->range = 0xFFFFFFFF;
}
static inline void rc_init_code(struct rc *rc)
{
int i;
for (i = 0; i < 5; i++) {
if (rc->ptr >= rc->buffer_end)
rc_read(rc);
rc->code = (rc->code << 8) | *rc->ptr++;
}
}
/* Called twice, but one callsite is in inline'd rc_is_bit_0_helper() */
static void rc_do_normalize(struct rc *rc)
{
if (rc->ptr >= rc->buffer_end)
rc_read(rc);
rc->range <<= 8;
rc->code = (rc->code << 8) | *rc->ptr++;
}
static inline void rc_normalize(struct rc *rc)
{
if (rc->range < (1 << RC_TOP_BITS))
rc_do_normalize(rc);
}
/* Called 9 times */
/* Why rc_is_bit_0_helper exists?
*Because we want to always expose (rc->code < rc->bound) to optimizer
*/
static inline unsigned int rc_is_bit_0_helper(struct rc *rc, unsigned short int *p)
{
rc_normalize(rc);
rc->bound = *p * (rc->range >> RC_MODEL_TOTAL_BITS);
return rc->bound;
}
static inline int rc_is_bit_0(struct rc *rc, unsigned short int *p)
{
unsigned int t = rc_is_bit_0_helper(rc, p);
return rc->code < t;
}
/* Called ~10 times, but very small, thus inlined */
static inline void rc_update_bit_0(struct rc *rc, unsigned short int *p)
{
rc->range = rc->bound;
*p += ((1 << RC_MODEL_TOTAL_BITS) - *p) >> RC_MOVE_BITS;
}
static inline void rc_update_bit_1(struct rc *rc, unsigned short int *p)
{
rc->range -= rc->bound;
rc->code -= rc->bound;
*p -= *p >> RC_MOVE_BITS;
}
/* Called 4 times in unlzma loop */
static int rc_get_bit(struct rc *rc, unsigned short int *p, int *symbol)
{
if (rc_is_bit_0(rc, p)) {
rc_update_bit_0(rc, p);
*symbol *= 2;
return 0;
} else {
rc_update_bit_1(rc, p);
*symbol = *symbol * 2 + 1;
return 1;
}
}
/* Called once */
static inline int rc_direct_bit(struct rc *rc)
{
rc_normalize(rc);
rc->range >>= 1;
if (rc->code >= rc->range) {
rc->code -= rc->range;
return 1;
}
return 0;
}
/* Called twice */
static inline void
rc_bit_tree_decode(struct rc *rc, unsigned short int *p, int num_levels, int *symbol)
{
int i = num_levels;
*symbol = 1;
while (i--)
rc_get_bit(rc, p + *symbol, symbol);
*symbol -= 1 << num_levels;
}
/*
* Small lzma deflate implementation.
* Copyright (C) 2006 Aurelien Jacobs < aurel@gnuage.org >
*
* Based on LzmaDecode.c from the LZMA SDK 4.22 (http://www.7-zip.org/)
* Copyright (C) 1999-2005 Igor Pavlov
*/
struct lzma_header {
unsigned char pos;
unsigned int dict_size;
unsigned long long int dst_size;
} __attribute__ ((packed)) ;
#define LZMA_BASE_SIZE 1846
#define LZMA_LIT_SIZE 768
#define LZMA_NUM_POS_BITS_MAX 4
#define LZMA_LEN_NUM_LOW_BITS 3
#define LZMA_LEN_NUM_MID_BITS 3
#define LZMA_LEN_NUM_HIGH_BITS 8
#define LZMA_LEN_CHOICE 0
#define LZMA_LEN_CHOICE_2 (LZMA_LEN_CHOICE + 1)
#define LZMA_LEN_LOW (LZMA_LEN_CHOICE_2 + 1)
#define LZMA_LEN_MID (LZMA_LEN_LOW \
+ (1 << (LZMA_NUM_POS_BITS_MAX + LZMA_LEN_NUM_LOW_BITS)))
#define LZMA_LEN_HIGH (LZMA_LEN_MID \
+(1 << (LZMA_NUM_POS_BITS_MAX + LZMA_LEN_NUM_MID_BITS)))
#define LZMA_NUM_LEN_PROBS (LZMA_LEN_HIGH + (1 << LZMA_LEN_NUM_HIGH_BITS))
#define LZMA_NUM_STATES 12
#define LZMA_NUM_LIT_STATES 7
#define LZMA_START_POS_MODEL_INDEX 4
#define LZMA_END_POS_MODEL_INDEX 14
#define LZMA_NUM_FULL_DISTANCES (1 << (LZMA_END_POS_MODEL_INDEX >> 1))
#define LZMA_NUM_POS_SLOT_BITS 6
#define LZMA_NUM_LEN_TO_POS_STATES 4
#define LZMA_NUM_ALIGN_BITS 4
#define LZMA_MATCH_MIN_LEN 2
#define LZMA_IS_MATCH 0
#define LZMA_IS_REP (LZMA_IS_MATCH + (LZMA_NUM_STATES << LZMA_NUM_POS_BITS_MAX))
#define LZMA_IS_REP_G0 (LZMA_IS_REP + LZMA_NUM_STATES)
#define LZMA_IS_REP_G1 (LZMA_IS_REP_G0 + LZMA_NUM_STATES)
#define LZMA_IS_REP_G2 (LZMA_IS_REP_G1 + LZMA_NUM_STATES)
#define LZMA_IS_REP_0_LONG (LZMA_IS_REP_G2 + LZMA_NUM_STATES)
#define LZMA_POS_SLOT (LZMA_IS_REP_0_LONG \
+ (LZMA_NUM_STATES << LZMA_NUM_POS_BITS_MAX))
#define LZMA_SPEC_POS (LZMA_POS_SLOT \
+(LZMA_NUM_LEN_TO_POS_STATES << LZMA_NUM_POS_SLOT_BITS))
#define LZMA_ALIGN (LZMA_SPEC_POS \
+ LZMA_NUM_FULL_DISTANCES - LZMA_END_POS_MODEL_INDEX)
#define LZMA_LEN_CODER (LZMA_ALIGN + (1 << LZMA_NUM_ALIGN_BITS))
#define LZMA_REP_LEN_CODER (LZMA_LEN_CODER + LZMA_NUM_LEN_PROBS)
#define LZMA_LITERAL (LZMA_REP_LEN_CODER + LZMA_NUM_LEN_PROBS)
struct writer {
unsigned char *buffer;
unsigned char previous_byte;
int buffer_pos;
int bufsize;
int global_pos;
int(*flush)(void*, unsigned int);
struct lzma_header *header;
};
struct cstate {
int state;
unsigned int rep0, rep1, rep2, rep3;
};
static inline int get_pos(struct writer *wr)
{
return
wr->global_pos + wr->buffer_pos;
}
static inline unsigned char peek_old_byte(struct writer *wr,
unsigned int offs)
{
if (!wr->flush) {
int pos;
while (offs > wr->header->dict_size)
offs -= wr->header->dict_size;
pos = wr->buffer_pos - offs;
return wr->buffer[pos];
} else {
unsigned int pos = wr->buffer_pos - offs;
while (pos >= wr->header->dict_size)
pos += wr->header->dict_size;
return wr->buffer[pos];
}
}
static inline int write_byte(struct writer *wr, unsigned char byte)
{
wr->buffer[wr->buffer_pos++] = wr->previous_byte = byte;
if (wr->flush && wr->buffer_pos == wr->header->dict_size) {
wr->buffer_pos = 0;
wr->global_pos += wr->header->dict_size;
if (wr->flush((char *)wr->buffer, wr->header->dict_size)
!= wr->header->dict_size)
return -1;
}
return 0;
}
static inline int copy_byte(struct writer *wr, unsigned int offs)
{
return write_byte(wr, peek_old_byte(wr, offs));
}
static inline int copy_bytes(struct writer *wr,
unsigned int rep0, int len)
{
do {
if (copy_byte(wr, rep0))
return -1;
len--;
} while (len != 0 && wr->buffer_pos < wr->header->dst_size);
return len;
}
static inline int process_bit0(struct writer *wr, struct rc *rc,
struct cstate *cst, unsigned short int *p,
int pos_state, unsigned short int *prob,
int lc, unsigned int literal_pos_mask) {
int mi = 1;
rc_update_bit_0(rc, prob);
prob = (p + LZMA_LITERAL +
(LZMA_LIT_SIZE
* (((get_pos(wr) & literal_pos_mask) << lc)
+ (wr->previous_byte >> (8 - lc))))
);
if (cst->state >= LZMA_NUM_LIT_STATES) {
int match_byte = peek_old_byte(wr, cst->rep0);
do {
int bit;
unsigned short int *prob_lit;
match_byte <<= 1;
bit = match_byte & 0x100;
prob_lit = prob + 0x100 + bit + mi;
if (rc_get_bit(rc, prob_lit, &mi)) {
if (!bit)
break;
} else {
if (bit)
break;
}
} while (mi < 0x100);
}
while (mi < 0x100) {
unsigned short int *prob_lit = prob + mi;
rc_get_bit(rc, prob_lit, &mi);
}
if (cst->state < 4)
cst->state = 0;
else if (cst->state < 10)
cst->state -= 3;
else
cst->state -= 6;
return write_byte(wr, mi);
}
static inline int process_bit1(struct writer *wr, struct rc *rc,
struct cstate *cst, unsigned short int *p,
int pos_state, unsigned short int *prob) {
int offset;
unsigned short int *prob_len;
int num_bits;
int len;
rc_update_bit_1(rc, prob);
prob = p + LZMA_IS_REP + cst->state;
if (rc_is_bit_0(rc, prob)) {
rc_update_bit_0(rc, prob);
cst->rep3 = cst->rep2;
cst->rep2 = cst->rep1;
cst->rep1 = cst->rep0;
cst->state = cst->state < LZMA_NUM_LIT_STATES ? 0 : 3;
prob = p + LZMA_LEN_CODER;
} else {
rc_update_bit_1(rc, prob);
prob = p + LZMA_IS_REP_G0 + cst->state;
if (rc_is_bit_0(rc, prob)) {
rc_update_bit_0(rc, prob);
prob = (p + LZMA_IS_REP_0_LONG
+ (cst->state <<
LZMA_NUM_POS_BITS_MAX) +
pos_state);
if (rc_is_bit_0(rc, prob)) {
rc_update_bit_0(rc, prob);
cst->state = cst->state < LZMA_NUM_LIT_STATES ?
9 : 11;
return copy_byte(wr, cst->rep0);
} else {
rc_update_bit_1(rc, prob);
}
} else {
unsigned int distance;
rc_update_bit_1(rc, prob);
prob = p + LZMA_IS_REP_G1 + cst->state;
if (rc_is_bit_0(rc, prob)) {
rc_update_bit_0(rc, prob);
distance = cst->rep1;
} else {
rc_update_bit_1(rc, prob);
prob = p + LZMA_IS_REP_G2 + cst->state;
if (rc_is_bit_0(rc, prob)) {
rc_update_bit_0(rc, prob);
distance = cst->rep2;
} else {
rc_update_bit_1(rc, prob);
distance = cst->rep3;
cst->rep3 = cst->rep2;
}
cst->rep2 = cst->rep1;
}
cst->rep1 = cst->rep0;
cst->rep0 = distance;
}
cst->state = cst->state < LZMA_NUM_LIT_STATES ? 8 : 11;
prob = p + LZMA_REP_LEN_CODER;
}
prob_len = prob + LZMA_LEN_CHOICE;
if (rc_is_bit_0(rc, prob_len)) {
rc_update_bit_0(rc, prob_len);
prob_len = (prob + LZMA_LEN_LOW
+ (pos_state <<
LZMA_LEN_NUM_LOW_BITS));
offset = 0;
num_bits = LZMA_LEN_NUM_LOW_BITS;
} else {
rc_update_bit_1(rc, prob_len);
prob_len = prob + LZMA_LEN_CHOICE_2;
if (rc_is_bit_0(rc, prob_len)) {
rc_update_bit_0(rc, prob_len);
prob_len = (prob + LZMA_LEN_MID
+ (pos_state <<
LZMA_LEN_NUM_MID_BITS));
offset = 1 << LZMA_LEN_NUM_LOW_BITS;
num_bits = LZMA_LEN_NUM_MID_BITS;
} else {
rc_update_bit_1(rc, prob_len);
prob_len = prob + LZMA_LEN_HIGH;
offset = ((1 << LZMA_LEN_NUM_LOW_BITS)
+ (1 << LZMA_LEN_NUM_MID_BITS));
num_bits = LZMA_LEN_NUM_HIGH_BITS;
}
}
rc_bit_tree_decode(rc, prob_len, num_bits, &len);
len += offset;
if (cst->state < 4) {
int pos_slot;
cst->state += LZMA_NUM_LIT_STATES;
prob =
p + LZMA_POS_SLOT +
((len <
LZMA_NUM_LEN_TO_POS_STATES ? len :
LZMA_NUM_LEN_TO_POS_STATES - 1)
<< LZMA_NUM_POS_SLOT_BITS);
rc_bit_tree_decode(rc, prob,
LZMA_NUM_POS_SLOT_BITS,
&pos_slot);
if (pos_slot >= LZMA_START_POS_MODEL_INDEX) {
int i, mi;
num_bits = (pos_slot >> 1) - 1;
cst->rep0 = 2 | (pos_slot & 1);
if (pos_slot < LZMA_END_POS_MODEL_INDEX) {
cst->rep0 <<= num_bits;
prob = p + LZMA_SPEC_POS +
cst->rep0 - pos_slot - 1;
} else {
num_bits -= LZMA_NUM_ALIGN_BITS;
while (num_bits--)
cst->rep0 = (cst->rep0 << 1) |
rc_direct_bit(rc);
prob = p + LZMA_ALIGN;
cst->rep0 <<= LZMA_NUM_ALIGN_BITS;
num_bits = LZMA_NUM_ALIGN_BITS;
}
i = 1;
mi = 1;
while (num_bits--) {
if (rc_get_bit(rc, prob + mi, &mi))
cst->rep0 |= i;
i <<= 1;
}
} else
cst->rep0 = pos_slot;
if (++(cst->rep0) == 0)
return 0;
if (cst->rep0 > wr->header->dict_size
|| cst->rep0 > get_pos(wr))
return -1;
}
len += LZMA_MATCH_MIN_LEN;
return copy_bytes(wr, cst->rep0, len);
}
int unlzma(unsigned char *buf, int in_len,
int(*fill)(void*, unsigned int),
int(*flush)(void*, unsigned int),
unsigned char *output,
int *posp,
void(*error)(char *x)
)
{
struct lzma_header header;
int lc, pb, lp;
unsigned int pos_state_mask;
unsigned int literal_pos_mask;
unsigned short int *p;
int num_probs;
struct rc rc;
int i, mi;
struct writer wr;
struct cstate cst;
unsigned char *inbuf;
int ret = -1;
rc.error = error;
if (buf)
inbuf = buf;
else
inbuf = malloc(LZMA_IOBUF_SIZE);
if (!inbuf) {
error("Could not allocate input bufer");
goto exit_0;
}
cst.state = 0;
cst.rep0 = cst.rep1 = cst.rep2 = cst.rep3 = 1;
wr.header = &header;
wr.flush = flush;
wr.global_pos = 0;
wr.previous_byte = 0;
wr.buffer_pos = 0;
rc_init(&rc, fill, inbuf, in_len);
for (i = 0; i < sizeof(header); i++) {
if (rc.ptr >= rc.buffer_end)
rc_read(&rc);
((unsigned char *)&header)[i] = *rc.ptr++;
}
if (header.pos >= (9 * 5 * 5)) {
error("bad header");
goto exit_1;
}
mi = 0;
lc = header.pos;
while (lc >= 9) {
mi++;
lc -= 9;
}
pb = 0;
lp = mi;
while (lp >= 5) {
pb++;
lp -= 5;
}
pos_state_mask = (1 << pb) - 1;
literal_pos_mask = (1 << lp) - 1;
ENDIAN_CONVERT(header.dict_size);
ENDIAN_CONVERT(header.dst_size);
if (header.dict_size == 0)
header.dict_size = 1;
if (output)
wr.buffer = output;
else {
wr.bufsize = MIN(header.dst_size, header.dict_size);
wr.buffer = malloc(wr.bufsize);
}
if (wr.buffer == NULL)
goto exit_1;
num_probs = LZMA_BASE_SIZE + (LZMA_LIT_SIZE << (lc + lp));
p = (unsigned short int *) malloc(num_probs * sizeof(*p));
if (p == 0)
goto exit_2;
num_probs = LZMA_LITERAL + (LZMA_LIT_SIZE << (lc + lp));
for (i = 0; i < num_probs; i++)
p[i] = (1 << RC_MODEL_TOTAL_BITS) >> 1;
rc_init_code(&rc);
while (get_pos(&wr) < header.dst_size) {
int pos_state = get_pos(&wr) & pos_state_mask;
unsigned short int *prob = p + LZMA_IS_MATCH +
(cst.state << LZMA_NUM_POS_BITS_MAX) + pos_state;
if (rc_is_bit_0(&rc, prob)) {
if (process_bit0(&wr, &rc, &cst, p, pos_state, prob,
lc, literal_pos_mask)) {
error("LZMA data is corrupt");
goto exit_3;
}
} else {
if (process_bit1(&wr, &rc, &cst, p, pos_state, prob)) {
error("LZMA data is corrupt");
goto exit_3;
}
if (cst.rep0 == 0)
break;
}
if (rc.buffer_size <= 0)
goto exit_3;
}
if (posp)
*posp = rc.ptr-rc.buffer;
if (!wr.flush || wr.flush(wr.buffer, wr.buffer_pos) == wr.buffer_pos)
ret = 0;
exit_3:
free(p);
exit_2:
if (!output)
free(wr.buffer);
exit_1:
if (!buf)
free(inbuf);
exit_0:
return ret;
}
int unlzma_simple(unsigned char *buf, int in_len,
unsigned char *output,
void(*error)(char *x))
{
return unlzma(buf, in_len, NULL, NULL, output, NULL, error);
}

131
src/gateware/zc706.py → src/zc706.py
View File

@ -1,10 +1,8 @@
#!/usr/bin/env python
import argparse
from operator import itemgetter
from migen import *
from migen.build.generic_platform import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from migen.genlib.cdc import MultiReg
from migen_axi.integration.soc_core import SoCCore
@ -15,10 +13,6 @@ from misoc.integration import cpu_interface
from artiq.gateware import rtio, nist_clock, nist_qc2
from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2
import dma
import analyzer
import acpki
class RTIOCRG(Module, AutoCSR):
def __init__(self, platform, rtio_internal_clk):
@ -65,18 +59,12 @@ class RTIOCRG(Module, AutoCSR):
class ZC706(SoCCore):
def __init__(self, acpki=False):
self.acpki = acpki
self.rustc_cfg = dict()
def __init__(self):
platform = zc706.Platform()
platform.toolchain.bitstream_commands.extend([
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
])
ident = self.__class__.__name__
if self.acpki:
ident = "acpki_" + ident
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=self.__class__.__name__)
platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
@ -92,81 +80,41 @@ class ZC706(SoCCore):
self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
self.csr_devices.append("rtio")
if self.acpki:
self.rustc_cfg["ki_impl"] = "acp"
self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
bus=self.ps7.s_axi_acp,
user=self.ps7.s_axi_acp_user,
evento=self.ps7.event.o)
self.csr_devices.append("rtio")
else:
self.rustc_cfg["ki_impl"] = "csr"
self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
self.csr_devices.append("rtio")
self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
self.csr_devices.append("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri],
[self.rtio_core.cri])
self.csr_devices.append("cri_con")
self.comb += self.rtio.cri.connect(self.rtio_core.cri)
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
self.ps7.s_axi_hp1)
self.csr_devices.append("rtio_analyzer")
class Simple(ZC706):
def __init__(self, **kwargs):
ZC706.__init__(self, **kwargs)
def __init__(self):
ZC706.__init__(self)
platform = self.platform
rtio_channels = []
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led", i))
pad = platform.request("user_led", i)
phy = ttl_simple.Output(pad)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.add_rtio(rtio_channels)
# The NIST backplanes require setting VADJ to 3.3V by reprogramming the power supply.
# This also changes the I/O standard for some on-board LEDs.
leds_fmc33 = [
("user_led_33", 0, Pins("Y21"), IOStandard("LVCMOS33")),
("user_led_33", 1, Pins("G2"), IOStandard("LVCMOS15")),
("user_led_33", 2, Pins("W21"), IOStandard("LVCMOS33")),
("user_led_33", 3, Pins("A17"), IOStandard("LVCMOS15")),
]
class NIST_CLOCK(ZC706):
"""
NIST clock hardware, with old backplane and 11 DDS channels
"""
def __init__(self, **kwargs):
ZC706.__init__(self, **kwargs)
def __init__(self):
ZC706.__init__(self)
platform = self.platform
platform.add_extension(nist_clock.fmc_adapter_io)
platform.add_extension(leds_fmc33)
rtio_channels = []
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led_33", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
for i in range(16):
if i % 4 == 3:
phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i))
@ -182,6 +130,10 @@ class NIST_CLOCK(ZC706):
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
phy = ttl_simple.Output(platform.request("user_led", 1))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
phy = ttl_simple.ClockGen(platform.request("la32_p"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
@ -196,9 +148,6 @@ class NIST_CLOCK(ZC706):
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.add_rtio(rtio_channels)
@ -207,19 +156,14 @@ class NIST_QC2(ZC706):
NIST QC2 hardware, as used in Quantum I and Quantum II, with new backplane
and 24 DDS channels. Two backplanes are used.
"""
def __init__(self, **kwargs):
ZC706.__init__(self, **kwargs)
def __init__(self):
ZC706.__init__(self)
platform = self.platform
platform.add_extension(nist_qc2.fmc_adapter_io)
platform.add_extension(leds_fmc33)
rtio_channels = []
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led_33", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
clock_generators = []
# All TTL channels are In+Out capable
for i in range(40):
@ -232,7 +176,14 @@ class NIST_QC2(ZC706):
phy = ttl_simple.ClockGen(
platform.request("clkout", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
clock_generators.append(rtio.Channel.from_phy(phy))
phy = ttl_simple.Output(platform.request("user_led", 1))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
# add clock generators after TTLs
rtio_channels += clock_generators
for i in range(4):
phy = spi2.SPIMaster(self.platform.request("spi", i))
@ -246,9 +197,6 @@ class NIST_QC2(ZC706):
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.add_rtio(rtio_channels)
@ -261,48 +209,31 @@ def write_csr_file(soc, filename):
soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))
def write_rustc_cfg_file(soc, filename):
with open(filename, "w") as f:
for k, v in sorted(soc.rustc_cfg.items(), key=itemgetter(0)):
if v is None:
f.write("{}\n".format(k))
else:
f.write("{}=\"{}\"\n".format(k, v))
def main():
parser = argparse.ArgumentParser(
description="ARTIQ port to the ZC706 Zynq development kit")
parser.add_argument("-r", default=None,
help="build Rust interface into the specified file")
parser.add_argument("-c", default=None,
help="build Rust compiler configuration into the specified file")
parser.add_argument("-g", default=None,
help="build gateware into the specified directory")
parser.add_argument("-V", "--variant", default="simple",
help="variant: "
"[acpki_]simple/nist_clock/nist_qc2 "
"simple/nist_clock/nist_qc2 "
"(default: %(default)s)")
args = parser.parse_args()
variant = args.variant.lower()
acpki = variant.startswith("acpki_")
if acpki:
variant = variant[6:]
try:
cls = VARIANTS[variant]
cls = VARIANTS[args.variant.lower()]
except KeyError:
raise SystemExit("Invalid variant (-V/--variant)")
soc = cls(acpki=acpki)
soc = cls()
soc.finalize()
if args.r is not None:
write_csr_file(soc, args.r)
if args.c is not None:
write_rustc_cfg_file(soc, args.c)
if args.g is not None:
soc.build(build_dir=args.g)
if args.r is not None:
write_csr_file(soc, args.r)
if __name__ == "__main__":

8
zynq-rs.nix
View File

@ -1,8 +0,0 @@
let
pkgs = import <nixpkgs> {};
in
pkgs.fetchgit {
url = "https://git.m-labs.hk/M-Labs/zynq-rs.git";
rev = "7360984efbd772ae992ef00af09786b0ae8430f0";
sha256 = "10xrkhvrs6p0pn50cccvbnzi7l9lp8a6xmqy0pv5vg0f1qq3zxif";
}