forked from M-Labs/artiq-zynq
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mem_protec
Author | SHA1 | Date | |
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d8f884a7b5 | |||
d62a89281d |
@ -17,19 +17,23 @@ MEMORY
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SECTIONS
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{
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.text :
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.text : ALIGN(0x1000000)
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{
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__text_start = .;
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KEEP(*(.text.exceptions));
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*(.text.boot);
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*(.text .text.*);
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__text_end = .;
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} > SDRAM
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.rodata : ALIGN(4)
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.rodata : ALIGN(0x1000000)
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{
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__rodata_start = .;
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*(.rodata .rodata.*);
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__rodata_end = .;
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} > SDRAM
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.data : ALIGN(4)
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.data : ALIGN(0x1000000)
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{
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*(.data .data.*);
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} > SDRAM
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@ -9,6 +9,7 @@ use libsupport_zynq::boot::Core1;
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use dyld;
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use crate::rpc;
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use crate::rtio;
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use crate::mem_protect;
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#[derive(Debug)]
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@ -316,6 +317,7 @@ pub fn main_core1() {
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// Flush data cache entries for the image in DDR, including
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// Memory/Instruction Symchronization Barriers
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dcci_slice(library.image.data);
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mem_protect::setup_core1(&library.image.data);
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core1_tx.send(Message::LoadCompleted);
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},
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@ -11,6 +11,7 @@ use log::{info, error};
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use libboard_zynq::{timer::GlobalTimer, logger, devc};
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use libsupport_zynq::ram;
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mod mem_protect;
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mod sd_reader;
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mod config;
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mod proto_core_io;
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@ -44,6 +45,7 @@ pub fn main_core0() {
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log::set_max_level(log::LevelFilter::Debug);
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info!("NAR3/Zynq7000 starting...");
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mem_protect::setup_core0();
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ram::init_alloc_linker();
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match config::Config::new() {
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71
src/runtime/src/mem_protect.rs
Normal file
71
src/runtime/src/mem_protect.rs
Normal file
@ -0,0 +1,71 @@
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use libcortex_a9::mmu::{AccessPermissions, L1_PAGE_SIZE, L1Table};
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/// Symbols defined by the linker script
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extern "C" {
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static __text_start: usize;
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static __text_end: usize;
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static __rodata_start: usize;
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static __rodata_end: usize;
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}
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/// Apply basic memory protection to the regions defined by the linker
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/// script for the runtime on core 0.
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///
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/// Therefore these regions need to be aligned to 1 MB.
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pub fn setup_core0() {
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let text_start = unsafe { &__text_start as *const _ as usize };
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let text_end = unsafe { &__text_end as *const _ as usize };
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let rodata_start = unsafe { &__rodata_start as *const _ as usize };
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let rodata_end = unsafe { &__rodata_end as *const _ as usize };
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let l1table = L1Table::get();
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for addr in (0..0xFFFF_FFFF).step_by(L1_PAGE_SIZE) {
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l1table.update(addr as *const usize, |l1section| {
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if addr >= text_start && addr < text_end {
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// Code: R-X
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l1section.access = AccessPermissions::ReadOnly;
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l1section.exec = true;
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} else if addr >= rodata_start && addr < rodata_end {
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// Data: R--
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l1section.access = AccessPermissions::ReadOnly;
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l1section.exec = false;
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} else {
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// Everything else: RW-
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l1section.access = AccessPermissions::FullAccess;
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l1section.exec = false;
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}
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});
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}
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}
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pub fn setup_core1(kernel_data: &[u8]) {
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let kernel_start = (&kernel_data[0] as *const _ as usize) & !(L1_PAGE_SIZE - 1);
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let kernel_end = ((&kernel_data[kernel_data.len() - 1] as *const _ as usize) | (L1_PAGE_SIZE - 1)) + 1;
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let text_start = unsafe { &__text_start as *const _ as usize };
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let text_end = unsafe { &__text_end as *const _ as usize };
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let rodata_start = unsafe { &__rodata_start as *const _ as usize };
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let rodata_end = unsafe { &__rodata_end as *const _ as usize };
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let l1table = L1Table::get();
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for addr in (0..0xFFFF_FFFF).step_by(L1_PAGE_SIZE) {
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l1table.update(addr as *const usize, |l1section| {
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if addr >= kernel_start && addr < kernel_end {
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// Kernel code/data: RWX
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l1section.access = AccessPermissions::FullAccess;
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l1section.exec = true;
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} else if addr >= text_start && addr < text_end {
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// Runtime code: R-X
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l1section.access = AccessPermissions::ReadOnly;
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l1section.exec = true;
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} else if addr >= rodata_start && addr < rodata_end {
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// Data: R--
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l1section.access = AccessPermissions::ReadOnly;
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l1section.exec = false;
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} else {
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// Everything else: RW-
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l1section.access = AccessPermissions::FullAccess;
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l1section.exec = false;
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}
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});
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}
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}
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