forked from M-Labs/artiq-zynq
Fixed incorrect byte_addr after multiple block read...
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da6bda9a06
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e4b17f9473
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@ -185,6 +185,7 @@ impl<'a> Read for SdReader<'a> {
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// we have to allow partial read, as per the trait required
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return Ok(a.len());
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}
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self.byte_addr += b.len() as u32;
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}
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if let Err(_) = self.read_unaligned(c) {
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// we have to allow partial read, as per the trait required
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@ -229,6 +230,7 @@ impl<'a> Write for SdReader<'a> {
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) {
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return Ok(a.len());
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}
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self.byte_addr += b.len() as u32;
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}
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if let Err(_) = self.write_unaligned(c) {
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return Ok(a.len() + b.len());
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@ -283,4 +285,3 @@ impl<'a> Drop for SdReader<'a> {
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self.flush().unwrap_or(());
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}
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}
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