cw
/
artiq-zynq
forked from M-Labs/artiq-zynq
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Fixed incorrect byte_addr after multiple block read...

This commit is contained in:
pca006132 2020-06-15 10:40:27 +08:00
parent da6bda9a06
commit e4b17f9473
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/runtime/src/sd_reader.rs
View File

@ -185,6 +185,7 @@ impl<'a> Read for SdReader<'a> {
// we have to allow partial read, as per the trait required // we have to allow partial read, as per the trait required
return Ok(a.len()); return Ok(a.len());
} }
self.byte_addr += b.len() as u32;
} }
if let Err(_) = self.read_unaligned(c) { if let Err(_) = self.read_unaligned(c) {
// we have to allow partial read, as per the trait required // we have to allow partial read, as per the trait required
@ -229,6 +230,7 @@ impl<'a> Write for SdReader<'a> {
) { ) {
return Ok(a.len()); return Ok(a.len());
} }
self.byte_addr += b.len() as u32;
} }
if let Err(_) = self.write_unaligned(c) { if let Err(_) = self.write_unaligned(c) {
return Ok(a.len() + b.len()); return Ok(a.len() + b.len());
@ -283,4 +285,3 @@ impl<'a> Drop for SdReader<'a> {
self.flush().unwrap_or(()); self.flush().unwrap_or(());
} }
} }