forked from M-Labs/artiq-zynq
more conservative RTIO PLL reset timing
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db2a8e7726
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d65e893d1c
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@ -116,11 +116,20 @@ fn init_rtio(timer: GlobalTimer, cfg: &config::Config) {
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unsafe {
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pl::csr::rtio_crg::pll_reset_write(1);
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pl::csr::rtio_crg::clock_sel_write(clock_sel);
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}
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let mut countdown = timer.countdown();
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countdown.start(Milliseconds(2));
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nb::block!(countdown.wait()).unwrap();
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unsafe {
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pl::csr::rtio_crg::pll_reset_write(0);
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}
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let mut countdown = timer.countdown();
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countdown.start(Milliseconds(1));
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countdown.start(Milliseconds(2));
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nb::block!(countdown.wait()).unwrap();
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let locked = unsafe { pl::csr::rtio_crg::pll_locked_read() != 0 };
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if !locked {
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panic!("RTIO PLL failed to lock");
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